Lines Matching refs:VIASR
289 val = uni_rd(sc, VIASR, SR30);
291 val = uni_rd(sc, VIASR, SR39);
652 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR, i);
653 bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR + 1,
679 uni_wr_mask(sc, VIASR, SR16, 0x00, BIT6);
715 uni_wr_mask(sc, VIASR, SR01, 0, BIT5);
721 uni_wr_mask(sc, VIASR, SR01, 0x20, BIT5);
948 uni_wr_mask(sc, VIASR, cridx, data, regmask);
1001 VIASR);
1042 uni_load_reg(sc, val, regnum, reg, VIASR);
1048 uni_load_reg(sc, val, regnum, reg, VIASR);
1054 uni_load_reg(sc, val, regnum, reg, VIASR);
1060 uni_load_reg(sc, val, regnum, reg, VIASR);
1079 uni_wr_mask(sc, VIASR, SR15, 0xae, 0xfe);
1082 uni_wr_mask(sc, VIASR, SR15, 0xb6, 0xfe);
1085 uni_wr_mask(sc, VIASR, SR15, 0x22, 0xfe);
1127 uni_wr(sc, VIASR, SR44, clk / 0x10000);
1128 uni_wr(sc, VIASR, SR45, (clk & 0xffff) / 0x100);
1129 uni_wr(sc, VIASR, SR46, clk % 0x100);
1143 uni_wr_mask(sc, VIASR, SR40, 0x02, BIT1);
1144 uni_wr_mask(sc, VIASR, SR40, 0x00, BIT1);
1162 uni_wr_mask(sc, VIASR, SR1A, 0x00, BIT0);
1163 uni_wr_mask(sc, VIASR, SR18, 0x00, BIT7+BIT6);
1168 uni_wr_mask(sc, VIASR, SR18, 0xc0, BIT7+BIT6);