Lines Matching refs:dc
71 pcitag_t tag, struct tga_devconfig *dc);
75 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc);
76 unsigned int tga_getdotclock(struct tga_devconfig *dc);
199 struct tga_devconfig *dc = &tmp_dc;
202 tga_mapaddrs(memt, pc, tag, &pcisize, dc);
203 dc->dc_tga_type = tga_identify(dc);
205 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type);
206 bus_space_unmap(memt, dc->dc_memh, pcisize);
207 if (dc->dc_tgaconf)
214 bus_size_t *pcisize, struct tga_devconfig *dc)
218 dc->dc_memt = memt;
219 dc->dc_tgaconf = NULL;
224 &dc->dc_pcipaddr, pcisize, &flags))
229 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize,
230 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh))
232 dc->dc_vaddr = (vaddr_t)bus_space_vaddr(memt, dc->dc_memh);
234 bus_space_subregion(dc->dc_memt, dc->dc_memh,
235 TGA_MEM_CREGS, TGA_CREGS_SIZE, &dc->dc_regs);
240 struct tga_devconfig *dc)
248 dc->dc_pc = pc;
249 dc->dc_pcitag = tag;
250 tga_mapaddrs(memt, pc, tag, &pcisize, dc);
251 dc->dc_tga_type = tga_identify(dc);
252 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type);
259 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) {
264 dc->dc_tga2 = 0;
269 dc->dc_tga2 = 1;
275 if (dc->dc_tga2)
276 tga2_init(dc);
278 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */
280 dc->dc_wid = 8192;
284 dc->dc_wid = 8196;
288 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */
296 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */
297 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */
298 TGAWREG(dc, TGA_REG_VHCR,
299 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001));
300 dc->dc_wid -= 4;
303 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8);
304 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */
307 TGAWREG(dc, TGA_REG_CCBR, 0);
308 TGAWREG(dc, TGA_REG_VVBR, 1);
309 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] +
311 dc->dc_blanked = 1;
312 tga_unblank(dc);
319 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff);
322 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(uint32_t))
323 *(uint32_t *)(dc->dc_videobase + i) = 0;
326 rip = &dc->dc_rinfo;
329 rip->ri_bits = (void *)dc->dc_videobase;
330 rip->ri_width = dc->dc_wid;
331 rip->ri_height = dc->dc_ht;
332 rip->ri_stride = dc->dc_rowbytes;
333 rip->ri_hw = dc;
334 if (dc == &tga_console_dc)
359 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font)) {
363 dc->dc_rinfo.ri_wsfcookie = cookie;
371 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows;
372 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows;
373 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols;
374 dc->dc_rinfo.ri_ops.copycols = tga_copycols;
375 dc->dc_rinfo.ri_ops.putchar = tga_putchar;
377 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows;
378 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols;
379 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops;
380 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps;
383 dc->dc_intrenabled = 0;
391 struct tga_devconfig *dc;
462 dc = sc->sc_dc;
463 dc->dc_ramdac_funcs = dc->dc_tgaconf->ramdac_funcs();
464 if (!dc->dc_tga2) {
465 if (dc->dc_tgaconf->ramdac_funcs == bt485_funcs)
466 dc->dc_ramdac_cookie =
467 dc->dc_ramdac_funcs->ramdac_register(dc,
470 dc->dc_ramdac_cookie =
471 dc->dc_ramdac_funcs->ramdac_register(dc,
474 dc->dc_ramdac_cookie = dc->dc_ramdac_funcs->ramdac_register(dc,
478 if (dc->dc_tgaconf->ramdac_funcs != bt485_funcs)
479 (*dc->dc_ramdac_funcs->ramdac_set_dotclock)
480 (dc->dc_ramdac_cookie, tga_getdotclock(dc));
488 (*dc->dc_ramdac_funcs->ramdac_init)(dc->dc_ramdac_cookie);
489 TGAWREG(dc, TGA_REG_SISR, 0x00000001); /* XXX */
491 if (dc->dc_tgaconf == NULL) {
495 aprint_normal("board type %s\n", dc->dc_tgaconf->tgac_name);
497 dc->dc_wid, dc->dc_ht,
498 dc->dc_tgaconf->tgac_phys_depth,
499 dc->dc_ramdac_funcs->ramdac_name);
528 struct tga_devconfig *dc = sc->sc_dc;
529 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
530 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
566 *(u_int *)data = dc->dc_blanked ?
591 *(u_int *)data = dc->dc_rowbytes;
597 return pci_devioctl(dc->dc_pc, dc->dc_pcitag,
601 return wsdisplayio_busid_pci(sc->sc_dev, dc->dc_pc,
602 dc->dc_pcitag, data);
610 struct tga_devconfig *dc = v;
612 if (dc->dc_intrenabled) {
617 dc->dc_ramdac_intr = f;
618 TGAWREG(dc, TGA_REG_SISR, 0x00010000);
621 TGAWREG(dc, TGA_REG_SISR, 0x00010001);
622 TGAREGWB(dc, TGA_REG_SISR, 1);
623 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0)
625 f(dc->dc_ramdac_cookie);
626 TGAWREG(dc, TGA_REG_SISR, 0x00000001);
627 TGAREGWB(dc, TGA_REG_SISR, 1);
636 struct tga_devconfig *dc = v;
637 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie;
641 reg = TGARREG(dc, TGA_REG_SISR);
646 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f));
647 TGAREGWB(dc, TGA_REG_SISR, 1);
659 if (dc->dc_ramdac_intr) {
660 dc->dc_ramdac_intr(dcrc);
661 dc->dc_ramdac_intr = NULL;
663 TGAWREG(dc, TGA_REG_SISR, 0x00000001);
664 TGAREGWB(dc, TGA_REG_SISR, 1);
767 tga_blank(struct tga_devconfig *dc)
770 if (!dc->dc_blanked) {
771 dc->dc_blanked = 1;
773 TGAWREG(dc, TGA_REG_VVVR,
774 TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK);
779 tga_unblank(struct tga_devconfig *dc)
782 if (dc->dc_blanked) {
783 dc->dc_blanked = 0;
785 TGAWREG(dc, TGA_REG_VVVR,
786 TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK);
794 tga_builtin_set_cursor(struct tga_devconfig *dc,
797 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
798 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
826 TGAWREG(dc, TGA_REG_VVVR,
827 TGARREG(dc, TGA_REG_VVVR) | 0x04);
830 TGAWREG(dc, TGA_REG_VVVR,
831 TGARREG(dc, TGA_REG_VVVR) & ~0x04);
834 TGAWREG(dc, TGA_REG_CXYR, ((cursorp->pos.y & 0xfff) << 12) |
842 TGAWREG(dc, TGA_REG_CCBR,
843 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) |
845 memcpy((void *)(dc->dc_vaddr +
846 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)),
853 tga_builtin_get_cursor(struct tga_devconfig *dc,
856 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
857 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
862 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0;
863 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff;
864 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff;
866 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f;
870 error = copyout((char *)(dc->dc_vaddr +
871 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)),
882 tga_builtin_set_curpos(struct tga_devconfig *dc,
886 TGAWREG(dc, TGA_REG_CXYR,
892 tga_builtin_get_curpos(struct tga_devconfig *dc,
896 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff;
897 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff;
902 tga_builtin_get_curmax(struct tga_devconfig *dc,
1025 struct tga_devconfig *dc = dst->ri_hw;
1031 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units;
1074 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */
1075 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */
1076 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */
1102 TGAWALREG(dc, TGA_REG_GCSR, 0,
1104 TGAWALREG(dc, TGA_REG_GCDR, 0,
1106 TGAWALREG(dc, TGA_REG_GCSR, 1,
1108 TGAWALREG(dc, TGA_REG_GCDR, 1,
1110 TGAWALREG(dc, TGA_REG_GCSR, 2,
1112 TGAWALREG(dc, TGA_REG_GCDR, 2,
1114 TGAWALREG(dc, TGA_REG_GCSR, 3,
1116 TGAWALREG(dc, TGA_REG_GCDR, 3,
1122 TGAWALREG(dc, TGA_REG_GCSR, 0,
1124 TGAWALREG(dc, TGA_REG_GCDR, 0,
1129 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */
1130 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */
1164 TGAWALREG(dc, TGA_REG_GCSR, 0,
1166 TGAWALREG(dc, TGA_REG_GCDR, 0,
1168 TGAWALREG(dc, TGA_REG_GCSR, 1,
1170 TGAWALREG(dc, TGA_REG_GCDR, 1,
1172 TGAWALREG(dc, TGA_REG_GCSR, 2,
1174 TGAWALREG(dc, TGA_REG_GCDR, 2,
1176 TGAWALREG(dc, TGA_REG_GCSR, 3,
1178 TGAWALREG(dc, TGA_REG_GCDR, 3,
1184 TGAWALREG(dc, TGA_REG_GCSR, 0,
1186 TGAWALREG(dc, TGA_REG_GCDR, 0,
1191 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */
1192 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */
1217 struct tga_devconfig *dc = ri->ri_hw;
1236 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]);
1237 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]);
1241 TGAWREG(dc, TGA_REG_GOPR, 0x3);
1243 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
1246 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1);
1249 TGAWREG(dc, TGA_REG_GMOR, 0x1);
1253 TGAREGWB(dc, TGA_REG_GMOR, 1);
1270 TGAWREG(dc, TGA_REG_GMOR, 0);
1271 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff);
1278 struct tga_devconfig *dc = ri->ri_hw;
1288 TGAWREG(dc, TGA_REG_GBCR0, color);
1289 TGAWREG(dc, TGA_REG_GBCR1, color);
1291 TGAWREG(dc, TGA_REG_GBCR2, color);
1292 TGAWREG(dc, TGA_REG_GBCR3, color);
1293 TGAWREG(dc, TGA_REG_GBCR4, color);
1294 TGAWREG(dc, TGA_REG_GBCR5, color);
1295 TGAWREG(dc, TGA_REG_GBCR6, color);
1296 TGAWREG(dc, TGA_REG_GBCR7, color);
1301 TGAWREG(dc, TGA_REG_GOPR, 0x3);
1303 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
1306 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff);
1309 TGAWREG(dc, TGA_REG_GMOR, 0x2d);
1313 TGAREGWB(dc, TGA_REG_GMOR, 1);
1321 TGAWREG(dc, TGA_REG_GMOR, 0);
1328 struct tga_devconfig *dc = ri->ri_hw;
1338 TGAWREG(dc, TGA_REG_GBCR0, color);
1339 TGAWREG(dc, TGA_REG_GBCR1, color);
1341 TGAWREG(dc, TGA_REG_GBCR2, color);
1342 TGAWREG(dc, TGA_REG_GBCR3, color);
1343 TGAWREG(dc, TGA_REG_GBCR4, color);
1344 TGAWREG(dc, TGA_REG_GBCR5, color);
1345 TGAWREG(dc, TGA_REG_GBCR6, color);
1346 TGAWREG(dc, TGA_REG_GBCR7, color);
1351 TGAWREG(dc, TGA_REG_GOPR, 0x3);
1353 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
1356 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff);
1359 TGAWREG(dc, TGA_REG_GMOR, 0x2d);
1363 TGAREGWB(dc, TGA_REG_GMOR, 1);
1371 TGAWREG(dc, TGA_REG_GMOR, 0);
1378 struct tga_devconfig *dc = v;
1383 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */
1384 TGAREGWB(dc, TGA_REG_EPDR, 1);
1390 struct tga_devconfig *dc = v;
1396 bus_space_subregion(dc->dc_memt, dc->dc_memh,
1398 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff);
1399 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE);
1405 struct tga_devconfig *dc = v;
1414 TGAREGWB(dc, TGA_REG_EPSR, 1);
1415 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1);
1416 TGAREGWB(dc, TGA_REG_EPSR, 1);
1417 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0);
1419 TGAREGRB(dc, TGA_REG_EPSR, 1);
1421 rdval = TGARREG(dc, TGA_REG_EPDR);
1422 TGAREGWB(dc, TGA_REG_EPSR, 1);
1423 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1);
1431 struct tga_devconfig *dc = v;
1443 TGAREGWB(dc, TGA_REG_EPDR, 1);
1444 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
1445 TGAREGWB(dc, TGA_REG_EPDR, 1);
1446 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val);
1447 TGAREGWB(dc, TGA_REG_EPDR, 1);
1448 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
1454 struct tga_devconfig *dc = v;
1460 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */
1461 TGAREGWB(dc, TGA_REG_EPSR, 1);
1463 rdval = TGARREG(dc, TGA_REG_EPDR);
1470 struct tga_devconfig *dc = v;
1477 bus_space_subregion(dc->dc_memt, dc->dc_memh,
1479 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff;
1480 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ);
1485 void tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock);
1487 struct monitor *tga_getmonitor(struct tga_devconfig *dc);
1490 tga2_init(struct tga_devconfig *dc)
1492 struct monitor *m = tga_getmonitor(dc);
1496 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) {
1501 tga2_ics9110_wr(dc, 14300000);
1508 tga2_ics9110_wr(dc, m->dotclock);
1511 TGAWREG(dc, TGA_REG_VHCR,
1517 TGAWREG(dc, TGA_REG_VHCR,
1523 TGAWREG(dc, TGA_REG_VVCR,
1528 TGAWREG(dc, TGA_REG_VVBR, 1);
1529 TGAREGRWB(dc, TGA_REG_VHCR, 3);
1530 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1);
1531 TGAREGRWB(dc, TGA_REG_VVVR, 1);
1532 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff);
1533 TGAREGRWB(dc, TGA_REG_GPMR, 1);
1537 tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock)
1588 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV +
1598 bus_space_write_4(dc->dc_memt, clock, 0, writeval);
1599 bus_space_barrier(dc->dc_memt, clock, 0, 4,
1602 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV +
1605 bus_space_write_4(dc->dc_memt, clock, 0, 0x0);
1606 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE);
1610 tga_getmonitor(struct tga_devconfig *dc)
1613 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f];
1617 tga_getdotclock(struct tga_devconfig *dc)
1620 return tga_getmonitor(dc)->dotclock;