Lines Matching refs:sv_write_indirect

246 sv_write_indirect(struct sv_softc *sc, uint8_t reg, uint8_t val)
401 sv_write_indirect(sc, SV_ANALOG_POWER_DOWN_CONTROL, 0);
402 sv_write_indirect(sc, SV_DIGITAL_POWER_DOWN_CONTROL, 0);
700 sv_write_indirect(sc, SV_PCM_SAMPLE_RATE_0, val & 0xff);
701 sv_write_indirect(sc, SV_PCM_SAMPLE_RATE_1, val >> 8);
762 sv_write_indirect(sc, SV_ADC_PLL_M, best_m);
763 sv_write_indirect(sc, SV_ADC_PLL_N,
800 sv_write_indirect(sc, SV_DMA_DATA_FORMAT, mode);
825 sv_write_indirect(sc, SV_DMAA_COUNT1, dma_count >> 8);
826 sv_write_indirect(sc, SV_DMAA_COUNT0, dma_count & 0xFF);
829 sv_write_indirect(sc, SV_PLAY_RECORD_ENABLE, mode | SV_PLAY_ENABLE);
855 sv_write_indirect(sc, SV_DMA_DATA_FORMAT, mode);
880 sv_write_indirect(sc, SV_DMAC_COUNT1, dma_count >> 8);
881 sv_write_indirect(sc, SV_DMAC_COUNT0, dma_count & 0xFF);
884 sv_write_indirect(sc, SV_PLAY_RECORD_ENABLE, mode | SV_RECORD_ENABLE);
898 sv_write_indirect(sc, SV_PLAY_RECORD_ENABLE, mode & ~SV_PLAY_ENABLE);
913 sv_write_indirect(sc, SV_PLAY_RECORD_ENABLE, mode & ~SV_RECORD_ENABLE);
1117 sv_write_indirect(sc, ports[idx].l_port, reg);
1125 sv_write_indirect(sc, ports[idx].r_port, reg);
1157 sv_write_indirect(sc, ports[idx].l_port, reg);
1167 sv_write_indirect(sc, ports[idx].r_port, reg);
1195 sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg);
1200 sv_write_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL, reg);
1221 sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg);
1226 sv_write_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL, reg);
1243 sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg);
1259 sv_write_indirect(sc, SV_SRS_SPACE_CONTROL, reg);