Lines Matching refs:REG_WR
797 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff);
896 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val);
897 REG_WR(sc, BNX_CTX_CTX_CTRL,
915 REG_WR(sc, BNX_CTX_DATA_ADR, offset);
916 REG_WR(sc, BNX_CTX_DATA, ctx_val);
956 REG_WR(sc, BNX_EMAC_MDIO_MODE, val);
965 REG_WR(sc, BNX_EMAC_MDIO_COMM, val);
996 REG_WR(sc, BNX_EMAC_MDIO_MODE, val);
1045 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1);
1054 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1);
1075 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1);
1142 REG_WR(sc, BNX_EMAC_MODE, val);
1164 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2);
1200 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2);
1235 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI);
1240 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);
1241 REG_WR(sc, BNX_NVM_COMMAND,
1278 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN);
1300 REG_WR(sc, BNX_NVM_ACCESS_ENABLE,
1322 REG_WR(sc, BNX_NVM_ACCESS_ENABLE,
1356 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);
1357 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE);
1358 REG_WR(sc, BNX_NVM_COMMAND, cmd);
1410 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);
1411 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE);
1412 REG_WR(sc, BNX_NVM_COMMAND, cmd);
1472 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);
1475 REG_WR(sc, BNX_NVM_WRITE, val32);
1476 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE);
1477 REG_WR(sc, BNX_NVM_COMMAND, cmd);
1571 REG_WR(sc, BNX_NVM_CFG1, flash->config1);
1572 REG_WR(sc, BNX_NVM_CFG2, flash->config2);
1573 REG_WR(sc, BNX_NVM_CFG3, flash->config3);
1574 REG_WR(sc, BNX_NVM_WRITE1, flash->write1);
2599 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code);
2601 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code);
2606 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val);
2609 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val);
2615 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET);
2617 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET);
3136 REG_WR(sc, BNX_CTX_COMMAND, val);
3155 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val |
3159 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val);
3160 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i |
3188 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0);
3189 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr);
3195 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr);
3196 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr);
3257 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val);
3262 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val);
3288 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff);
3322 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS,
3334 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val);
3354 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET);
3367 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val);
3423 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT);
3451 REG_WR(sc, BNX_DMA_CONFIG, val);
3461 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS,
3490 REG_WR(sc, BNX_MQ_CONFIG, val);
3493 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val);
3494 REG_WR(sc, BNX_MQ_KNL_WIND_END, val);
3497 REG_WR(sc, BNX_RV2P_CONFIG, val);
3503 REG_WR(sc, BNX_TBDR_CONFIG, val);
3536 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val);
3542 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK);
3543 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3546 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr));
3547 REG_WR(sc, BNX_HC_STATUS_ADDR_H,
3551 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L,
3553 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H,
3557 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int
3559 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int
3561 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) |
3563 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) |
3565 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) |
3567 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) |
3569 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) |
3571 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00));
3572 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3573 REG_WR(sc, BNX_HC_CONFIG,
3578 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW);
3614 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val);
3622 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS,
3625 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT);
3628 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff);
4107 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM);
4183 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
4266 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD,
4270 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD,
4277 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE);
4589 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
4725 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT);
4740 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID |
4743 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID |
4747 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW);
4802 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu |
5073 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5209 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD,
5280 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD,
5283 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD,
5341 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4),
5361 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4),
5373 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode);
5377 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0);
5378 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode);
5379 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA);