Lines Matching refs:ctl
38 volatile u_char ctl;
55 zs->ctl = 1; rr1 = zs->ctl;
56 zs->ctl = 0;
57 if ((rr1 & 0x1) == 1 && (zs->ctl & 0x4) == 4)
60 zs->ctl = 9;
61 zs->ctl = 0x00; /* clear interrupt */
62 zs->ctl = 4;
63 zs->ctl = 0x44; /* 16x clk, 1 stop bit */
64 zs->ctl = 5;
65 zs->ctl = 0xea; /* DTR on, 8 bit xmit, xmit on, RTS on */
66 zs->ctl = 3;
67 zs->ctl = 0xc1; /* 8 bit recv, auto cd_cts, recv on */
68 zs->ctl = 1;
69 zs->ctl = 0x00; /* no intrs */
70 zs->ctl = 2;
71 zs->ctl = 0x00; /* no vector */
72 zs->ctl = 10;
73 zs->ctl = 0x00; /* */
74 zs->ctl = 11;
75 zs->ctl = 0x50; /* clocking options */
76 zs->ctl = 12;
77 zs->ctl = 0x0e; /* 9600 baud, part 1 */
78 zs->ctl = 13;
79 zs->ctl = 0x00; /* 9600 baud, part 2 */
80 zs->ctl = 14;
81 zs->ctl = 0x03; /* more clocking options */
82 zs->ctl = 15;
83 zs->ctl = 0x00; /* clear intrs */
94 zs->ctl = 0;
95 while ((zs->ctl & 0x04) == 0) {
96 zs->ctl = 0;
98 zs->ctl = 8;
99 zs->ctl = (char)c;
109 zs->ctl = 0;
110 while ((zs->ctl & 0x1) == 0) {
111 zs->ctl = 0;
113 zs->ctl = 8;
114 return zs->ctl;