arm/omap/omap_gpio.c

70 	bus_space_tag_t sc_bust;
109 	sc->sc_bust = tipb->tipb_iot;
119 	if (bus_space_map(sc->sc_bust, tipb->tipb_addr, tipb->tipb_size, 0,
130 	reg = bus_space_read_4(sc->sc_bust, sc->sc_bush, GPIO_SYSCONFIG);
131 	bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_SYSCONFIG,
134 		reg = bus_space_read_4(sc->sc_bust, sc->sc_bush,
141 	reg = bus_space_read_4(sc->sc_bust, sc->sc_bush, GPIO_SYSCONFIG);
143 	bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_SYSCONFIG,
175 	reg = bus_space_read_4(sc->sc_bust, sc->sc_bush, GPIO_DIRECTION);
198 	reg = bus_space_read_4(sc->sc_bust, sc->sc_bush,
203 		bus_space_write_4(sc->sc_bust, sc->sc_bush,
207 		bus_space_write_4(sc->sc_bust, sc->sc_bush,
224 	return (bus_space_read_4(sc->sc_bust, sc->sc_bush,
241 		bus_space_write_4(sc->sc_bust, sc->sc_bush,
244 		bus_space_write_4(sc->sc_bust, sc->sc_bush,
324 	levelreg = bus_space_read_4(sc->sc_bust, sc->sc_bush, reg);
326  	bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, levelreg);
329 	bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_IRQSTATUS, bit);
333 	bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, levelreg);
336 	bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_CLEAR_WAKEUPENA,
340 	bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_SET_IRQENABLE,
363 	bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_CLEAR_WAKEUPENA,
367 	bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_CLEAR_IRQENABLE,
393 	bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_CLEAR_IRQENABLE,
415 	bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_SET_IRQENABLE,
437 		bus_space_write_4(sc->sc_bust, sc->sc_bush,
440 		bus_space_write_4(sc->sc_bust, sc->sc_bush,
453 	irqs = bus_space_read_4(sc->sc_bust, sc->sc_bush, GPIO_IRQSTATUS);
455  	bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_IRQSTATUS, irqs);
492 		irqs = bus_space_read_4(sc->sc_bust, sc->sc_bush, GPIO_IRQSTATUS);
505 		bus_space_write_4(sc->sc_bust, sc->sc_bush, GPIO_IRQSTATUS, irqs);