Lines Matching refs:input_port
575 { "pll", ENC(0, 0), 0, input_port, },
576 { "dma_stat", ENC(0, 1), 0, input_port, },
577 { "ppi@0", ENC(0, 2), 0, input_port, },
578 { "sport@0_stat", ENC(0, 3), 0, input_port, },
579 { "sport@1_stat", ENC(0, 4), 0, input_port, },
580 { "uart2@0_stat", ENC(0, 5), 0, input_port, },
581 { "uart2@1_stat", ENC(0, 6), 0, input_port, },
582 { "spi@0", ENC(0, 7), 0, input_port, },
583 { "spi@1", ENC(0, 8), 0, input_port, },
584 { "can_stat", ENC(0, 9), 0, input_port, },
585 { "rsi_int0", ENC(0, 10), 0, input_port, },
586 /*{ "reserved", ENC(0, 11), 0, input_port, },*/
587 { "counter@0", ENC(0, 12), 0, input_port, },
588 { "counter@1", ENC(0, 13), 0, input_port, },
589 { "dma@0", ENC(0, 14), 0, input_port, },
590 { "dma@1", ENC(0, 15), 0, input_port, },
591 { "dma@2", ENC(0, 16), 0, input_port, },
592 { "dma@3", ENC(0, 17), 0, input_port, },
593 { "dma@4", ENC(0, 18), 0, input_port, },
594 { "dma@5", ENC(0, 19), 0, input_port, },
595 { "dma@6", ENC(0, 20), 0, input_port, },
596 { "dma@7", ENC(0, 21), 0, input_port, },
597 { "dma@8", ENC(0, 22), 0, input_port, },
598 { "dma@9", ENC(0, 23), 0, input_port, },
599 { "dma@10", ENC(0, 24), 0, input_port, },
600 { "dma@11", ENC(0, 25), 0, input_port, },
601 { "can_rx", ENC(0, 26), 0, input_port, },
602 { "can_tx", ENC(0, 27), 0, input_port, },
603 { "twi@0", ENC(0, 28), 0, input_port, },
604 { "portf_irq_a", ENC(0, 29), 0, input_port, },
605 { "portf_irq_b", ENC(0, 30), 0, input_port, },
606 /*{ "reserved", ENC(0, 31), 0, input_port, },*/
608 { "gptimer@0", ENC(1, 0), 0, input_port, },
609 { "gptimer@1", ENC(1, 1), 0, input_port, },
610 { "gptimer@2", ENC(1, 2), 0, input_port, },
611 { "gptimer@3", ENC(1, 3), 0, input_port, },
612 { "gptimer@4", ENC(1, 4), 0, input_port, },
613 { "gptimer@5", ENC(1, 5), 0, input_port, },
614 { "gptimer@6", ENC(1, 6), 0, input_port, },
615 { "gptimer@7", ENC(1, 7), 0, input_port, },
616 { "portg_irq_a", ENC(1, 8), 0, input_port, },
617 { "portg_irq_b", ENC(1, 9), 0, input_port, },
618 { "mdma@0", ENC(1, 10), 0, input_port, },
619 { "mdma@1", ENC(1, 11), 0, input_port, },
620 { "wdog", ENC(1, 12), 0, input_port, },
621 { "porth_irq_a", ENC(1, 13), 0, input_port, },
622 { "porth_irq_b", ENC(1, 14), 0, input_port, },
623 { "acm_stat", ENC(1, 15), 0, input_port, },
624 { "acm_int", ENC(1, 16), 0, input_port, },
625 /*{ "reserved", ENC(1, 17), 0, input_port, },*/
626 /*{ "reserved", ENC(1, 18), 0, input_port, },*/
627 { "pwm@0_trip", ENC(1, 19), 0, input_port, },
628 { "pwm@0_sync", ENC(1, 20), 0, input_port, },
629 { "pwm@1_trip", ENC(1, 21), 0, input_port, },
630 { "pwm@1_sync", ENC(1, 22), 0, input_port, },
631 { "rsi_int1", ENC(1, 23), 0, input_port, },
639 { "pll", ENC(0, 0), 0, input_port, },
640 { "dma_stat", ENC(0, 1), 0, input_port, },
641 { "dmar0_block", ENC(0, 2), 0, input_port, },
642 { "dmar1_block", ENC(0, 3), 0, input_port, },
643 { "dmar0_over", ENC(0, 4), 0, input_port, },
644 { "dmar1_over", ENC(0, 5), 0, input_port, },
645 { "ppi@0", ENC(0, 6), 0, input_port, },
646 { "emac_stat", ENC(0, 7), 0, input_port, },
647 { "sport@0_stat", ENC(0, 8), 0, input_port, },
648 { "sport@1_stat", ENC(0, 9), 0, input_port, },
649 { "ptp_err", ENC(0, 10), 0, input_port, },
650 /*{ "reserved", ENC(0, 11), 0, input_port, },*/
651 { "uart@0_stat", ENC(0, 12), 0, input_port, },
652 { "uart@1_stat", ENC(0, 13), 0, input_port, },
653 { "rtc", ENC(0, 14), 0, input_port, },
654 { "dma@0", ENC(0, 15), 0, input_port, },
655 { "dma@3", ENC(0, 16), 0, input_port, },
656 { "dma@4", ENC(0, 17), 0, input_port, },
657 { "dma@5", ENC(0, 18), 0, input_port, },
658 { "dma@6", ENC(0, 19), 0, input_port, },
659 { "twi@0", ENC(0, 20), 0, input_port, },
660 { "dma@7", ENC(0, 21), 0, input_port, },
661 { "dma@8", ENC(0, 22), 0, input_port, },
662 { "dma@9", ENC(0, 23), 0, input_port, },
663 { "dma@10", ENC(0, 24), 0, input_port, },
664 { "dma@11", ENC(0, 25), 0, input_port, },
665 { "otp", ENC(0, 26), 0, input_port, },
666 { "counter", ENC(0, 27), 0, input_port, },
667 { "dma@1", ENC(0, 28), 0, input_port, },
668 { "porth_irq_a", ENC(0, 29), 0, input_port, },
669 { "dma@2", ENC(0, 30), 0, input_port, },
670 { "porth_irq_b", ENC(0, 31), 0, input_port, },
672 { "gptimer@0", ENC(1, 0), 0, input_port, },
673 { "gptimer@1", ENC(1, 1), 0, input_port, },
674 { "gptimer@2", ENC(1, 2), 0, input_port, },
675 { "gptimer@3", ENC(1, 3), 0, input_port, },
676 { "gptimer@4", ENC(1, 4), 0, input_port, },
677 { "gptimer@5", ENC(1, 5), 0, input_port, },
678 { "gptimer@6", ENC(1, 6), 0, input_port, },
679 { "gptimer@7", ENC(1, 7), 0, input_port, },
680 { "portg_irq_a", ENC(1, 8), 0, input_port, },
681 { "portg_irq_b", ENC(1, 9), 0, input_port, },
682 { "mdma@0", ENC(1, 10), 0, input_port, },
683 { "mdma@1", ENC(1, 11), 0, input_port, },
684 { "wdog", ENC(1, 12), 0, input_port, },
685 { "portf_irq_a", ENC(1, 13), 0, input_port, },
686 { "portf_irq_b", ENC(1, 14), 0, input_port, },
687 { "spi@0", ENC(1, 15), 0, input_port, },
688 { "spi@1", ENC(1, 16), 0, input_port, },
689 /*{ "reserved", ENC(1, 17), 0, input_port, },*/
690 /*{ "reserved", ENC(1, 18), 0, input_port, },*/
691 { "rsi_int0", ENC(1, 19), 0, input_port, },
692 { "rsi_int1", ENC(1, 20), 0, input_port, },
693 { "pwm_trip", ENC(1, 21), 0, input_port, },
694 { "pwm_sync", ENC(1, 22), 0, input_port, },
695 { "ptp_stat", ENC(1, 23), 0, input_port, },
703 { "pll", ENC(0, 0), 0, input_port, },
704 { "dma_stat", ENC(0, 1), 0, input_port, },
705 { "dmar0_block", ENC(0, 2), 0, input_port, },
706 { "dmar1_block", ENC(0, 3), 0, input_port, },
707 { "dmar0_over", ENC(0, 4), 0, input_port, },
708 { "dmar1_over", ENC(0, 5), 0, input_port, },
709 { "ppi@0", ENC(0, 6), 0, input_port, },
710 { "emac_stat", ENC(0, 7), 0, input_port, },
711 { "sport@0_stat", ENC(0, 8), 0, input_port, },
712 { "sport@1_stat", ENC(0, 9), 0, input_port, },
713 /*{ "reserved", ENC(0, 10), 0, input_port, },*/
714 /*{ "reserved", ENC(0, 11), 0, input_port, },*/
715 { "uart@0_stat", ENC(0, 12), 0, input_port, },
716 { "uart@1_stat", ENC(0, 13), 0, input_port, },
717 { "rtc", ENC(0, 14), 0, input_port, },
718 { "dma@0", ENC(0, 15), 0, input_port, },
719 { "dma@3", ENC(0, 16), 0, input_port, },
720 { "dma@4", ENC(0, 17), 0, input_port, },
721 { "dma@5", ENC(0, 18), 0, input_port, },
722 { "dma@6", ENC(0, 19), 0, input_port, },
723 { "twi@0", ENC(0, 20), 0, input_port, },
724 { "dma@7", ENC(0, 21), 0, input_port, },
725 { "dma@8", ENC(0, 22), 0, input_port, },
726 { "dma@9", ENC(0, 23), 0, input_port, },
727 { "dma@10", ENC(0, 24), 0, input_port, },
728 { "dma@11", ENC(0, 25), 0, input_port, },
729 { "otp", ENC(0, 26), 0, input_port, },
730 { "counter", ENC(0, 27), 0, input_port, },
731 { "dma@1", ENC(0, 28), 0, input_port, },
732 { "porth_irq_a", ENC(0, 29), 0, input_port, },
733 { "dma@2", ENC(0, 30), 0, input_port, },
734 { "porth_irq_b", ENC(0, 31), 0, input_port, },
736 { "gptimer@0", ENC(1, 0), 0, input_port, },
737 { "gptimer@1", ENC(1, 1), 0, input_port, },
738 { "gptimer@2", ENC(1, 2), 0, input_port, },
739 { "gptimer@3", ENC(1, 3), 0, input_port, },
740 { "gptimer@4", ENC(1, 4), 0, input_port, },
741 { "gptimer@5", ENC(1, 5), 0, input_port, },
742 { "gptimer@6", ENC(1, 6), 0, input_port, },
743 { "gptimer@7", ENC(1, 7), 0, input_port, },
744 { "portg_irq_a", ENC(1, 8), 0, input_port, },
745 { "portg_irq_b", ENC(1, 9), 0, input_port, },
746 { "mdma@0", ENC(1, 10), 0, input_port, },
747 { "mdma@1", ENC(1, 11), 0, input_port, },
748 { "wdog", ENC(1, 12), 0, input_port, },
749 { "portf_irq_a", ENC(1, 13), 0, input_port, },
750 { "portf_irq_b", ENC(1, 14), 0, input_port, },
751 { "spi@0", ENC(1, 15), 0, input_port, },
752 { "nfc_stat", ENC(1, 16), 0, input_port, },
753 { "hostdp_stat", ENC(1, 17), 0, input_port, },
754 { "hostdp_done", ENC(1, 18), 0, input_port, },
755 { "usb_int0", ENC(1, 20), 0, input_port, },
756 { "usb_int1", ENC(1, 21), 0, input_port, },
757 { "usb_int2", ENC(1, 22), 0, input_port, },
793 { "pll", ENC(0, 0), 0, input_port, },
794 { "dma_stat", ENC(0, 1), 0, input_port, },
795 { "ppi@0", ENC(0, 2), 0, input_port, },
796 { "sport@0_stat", ENC(0, 3), 0, input_port, },
797 { "sport@1_stat", ENC(0, 4), 0, input_port, },
798 { "spi@0", ENC(0, 5), 0, input_port, },
799 { "uart@0_stat", ENC(0, 6), 0, input_port, },
800 { "rtc", ENC(0, 7), 0, input_port, },
801 { "dma@0", ENC(0, 8), 0, input_port, },
802 { "dma@1", ENC(0, 9), 0, input_port, },
803 { "dma@2", ENC(0, 10), 0, input_port, },
804 { "dma@3", ENC(0, 11), 0, input_port, },
805 { "dma@4", ENC(0, 12), 0, input_port, },
806 { "dma@5", ENC(0, 13), 0, input_port, },
807 { "dma@6", ENC(0, 14), 0, input_port, },
808 { "dma@7", ENC(0, 15), 0, input_port, },
809 { "gptimer@0", ENC(0, 16), 0, input_port, },
810 { "gptimer@1", ENC(0, 17), 0, input_port, },
811 { "gptimer@2", ENC(0, 18), 0, input_port, },
812 { "portf_irq_a", ENC(0, 19), 0, input_port, },
813 { "portf_irq_b", ENC(0, 20), 0, input_port, },
814 { "mdma@0", ENC(0, 21), 0, input_port, },
815 { "mdma@1", ENC(0, 22), 0, input_port, },
816 { "wdog", ENC(0, 23), 0, input_port, },
826 { "pll", ENC(0, 0), 0, input_port, },
827 { "dma_stat", ENC(0, 1), 0, input_port, },
828 { "dmar0_block", ENC(1, 1), 0, input_port, },
829 { "dmar1_block", ENC(2, 1), 0, input_port, },
830 { "dmar0_over", ENC(3, 1), 0, input_port, },
831 { "dmar1_over", ENC(4, 1), 0, input_port, },
832 { "can_stat", ENC(0, 2), 0, input_port, },
833 { "emac_stat", ENC(1, 2), 0, input_port, },
834 { "sport@0_stat", ENC(2, 2), 0, input_port, },
835 { "sport@1_stat", ENC(3, 2), 0, input_port, },
836 { "ppi@0", ENC(4, 2), 0, input_port, },
837 { "spi@0", ENC(5, 2), 0, input_port, },
838 { "uart@0_stat", ENC(6, 2), 0, input_port, },
839 { "uart@1_stat", ENC(7, 2), 0, input_port, },
840 { "rtc", ENC(0, 3), 0, input_port, },
841 { "dma@0", ENC(0, 4), 0, input_port, },
842 { "dma@3", ENC(0, 5), 0, input_port, },
843 { "dma@4", ENC(0, 6), 0, input_port, },
844 { "dma@5", ENC(0, 7), 0, input_port, },
845 { "dma@6", ENC(0, 8), 0, input_port, },
846 { "twi@0", ENC(0, 9), 0, input_port, },
847 { "dma@7", ENC(0, 10), 0, input_port, },
848 { "dma@8", ENC(0, 11), 0, input_port, },
849 { "dma@9", ENC(0, 12), 0, input_port, },
850 { "dma@10", ENC(0, 13), 0, input_port, },
851 { "dma@11", ENC(0, 14), 0, input_port, },
852 { "can_rx", ENC(0, 15), 0, input_port, },
853 { "can_tx", ENC(0, 16), 0, input_port, },
854 { "dma@1", ENC(0, 17), 0, input_port, },
855 { "porth_irq_a", ENC(1, 17), 0, input_port, },
856 { "dma@2", ENC(0, 18), 0, input_port, },
857 { "porth_irq_b", ENC(1, 18), 0, input_port, },
858 { "gptimer@0", ENC(0, 19), 0, input_port, },
859 { "gptimer@1", ENC(0, 20), 0, input_port, },
860 { "gptimer@2", ENC(0, 21), 0, input_port, },
861 { "gptimer@3", ENC(0, 22), 0, input_port, },
862 { "gptimer@4", ENC(0, 23), 0, input_port, },
863 { "gptimer@5", ENC(0, 24), 0, input_port, },
864 { "gptimer@6", ENC(0, 25), 0, input_port, },
865 { "gptimer@7", ENC(0, 26), 0, input_port, },
866 { "portf_irq_a", ENC(0, 27), 0, input_port, },
867 { "portg_irq_a", ENC(1, 27), 0, input_port, },
868 { "portg_irq_b", ENC(0, 28), 0, input_port, },
869 { "mdma@0", ENC(0, 29), 0, input_port, },
870 { "mdma@1", ENC(0, 30), 0, input_port, },
871 { "wdog", ENC(0, 31), 0, input_port, },
872 { "portf_irq_b", ENC(1, 31), 0, input_port, },
903 { "pll", ENC(0, 0), 0, input_port, },
904 { "dmac@0_stat", ENC(0, 1), 0, input_port, },
905 { "ppi@0", ENC(0, 2), 0, input_port, },
906 { "sport@0_stat", ENC(0, 3), 0, input_port, },
907 { "sport@1_stat", ENC(0, 4), 0, input_port, },
908 { "spi@0", ENC(0, 5), 0, input_port, },
909 { "uart@0_stat", ENC(0, 6), 0, input_port, },
910 { "rtc", ENC(0, 7), 0, input_port, },
911 { "dma@0", ENC(0, 8), 0, input_port, },
912 { "dma@1", ENC(0, 9), 0, input_port, },
913 { "dma@2", ENC(0, 10), 0, input_port, },
914 { "dma@3", ENC(0, 11), 0, input_port, },
915 { "dma@4", ENC(0, 12), 0, input_port, },
916 { "dma@5", ENC(0, 13), 0, input_port, },
917 { "dma@6", ENC(0, 14), 0, input_port, },
918 { "dma@7", ENC(0, 15), 0, input_port, },
919 { "gptimer@0", ENC(0, 16), 0, input_port, },
920 { "gptimer@1", ENC(0, 17), 0, input_port, },
921 { "gptimer@2", ENC(0, 18), 0, input_port, },
922 { "portf_irq_a", ENC(0, 19), 0, input_port, },
923 { "portf_irq_b", ENC(0, 20), 0, input_port, },
924 { "mdma@0", ENC(0, 21), 0, input_port, },
925 { "mdma@1", ENC(0, 22), 0, input_port, },
926 { "wdog", ENC(0, 23), 0, input_port, },
927 { "dmac@1_stat", ENC(0, 24), 0, input_port, },
928 { "sport@2_stat", ENC(0, 25), 0, input_port, },
929 { "sport@3_stat", ENC(0, 26), 0, input_port, },
930 /*{ "reserved", ENC(0, 27), 0, input_port, },*/
931 { "spi@1", ENC(0, 28), 0, input_port, },
932 { "spi@2", ENC(0, 29), 0, input_port, },
933 { "uart@1_stat", ENC(0, 30), 0, input_port, },
934 { "uart@2_stat", ENC(0, 31), 0, input_port, },
936 { "can_stat", ENC(1, 0), 0, input_port, },
937 { "dma@8", ENC(1, 1), 0, input_port, },
938 { "dma@9", ENC(1, 2), 0, input_port, },
939 { "dma@10", ENC(1, 3), 0, input_port, },
940 { "dma@11", ENC(1, 4), 0, input_port, },
941 { "dma@12", ENC(1, 5), 0, input_port, },
942 { "dma@13", ENC(1, 6), 0, input_port, },
943 { "dma@14", ENC(1, 7), 0, input_port, },
944 { "dma@15", ENC(1, 8), 0, input_port, },
945 { "dma@16", ENC(1, 9), 0, input_port, },
946 { "dma@17", ENC(1, 10), 0, input_port, },
947 { "dma@18", ENC(1, 11), 0, input_port, },
948 { "dma@19", ENC(1, 12), 0, input_port, },
949 { "twi@0", ENC(1, 13), 0, input_port, },
950 { "twi@1", ENC(1, 14), 0, input_port, },
951 { "can_rx", ENC(1, 15), 0, input_port, },
952 { "can_tx", ENC(1, 16), 0, input_port, },
953 { "mdma@2", ENC(1, 17), 0, input_port, },
954 { "mdma@3", ENC(1, 18), 0, input_port, },
962 { "pll", ENC(0, 0), 0, input_port, },
963 { "dmac@0_stat", ENC(0, 1), 0, input_port, },
964 { "eppi@0", ENC(0, 2), 0, input_port, },
965 { "sport@0_stat", ENC(0, 3), 0, input_port, },
966 { "sport@1_stat", ENC(0, 4), 0, input_port, },
967 { "spi@0", ENC(0, 5), 0, input_port, },
968 { "uart2@0_stat", ENC(0, 6), 0, input_port, },
969 { "rtc", ENC(0, 7), 0, input_port, },
970 { "dma@12", ENC(0, 8), 0, input_port, },
971 { "dma@0", ENC(0, 9), 0, input_port, },
972 { "dma@1", ENC(0, 10), 0, input_port, },
973 { "dma@2", ENC(0, 11), 0, input_port, },
974 { "dma@3", ENC(0, 12), 0, input_port, },
975 { "dma@4", ENC(0, 13), 0, input_port, },
976 { "dma@6", ENC(0, 14), 0, input_port, },
977 { "dma@7", ENC(0, 15), 0, input_port, },
978 { "gptimer@8", ENC(0, 16), 0, input_port, },
979 { "gptimer@9", ENC(0, 17), 0, input_port, },
980 { "gptimer@10", ENC(0, 18), 0, input_port, },
981 { "pint@0", ENC(0, 19), 0, input_port, },
982 { "pint@1", ENC(0, 20), 0, input_port, },
983 { "mdma@0", ENC(0, 21), 0, input_port, },
984 { "mdma@1", ENC(0, 22), 0, input_port, },
985 { "wdog", ENC(0, 23), 0, input_port, },
986 { "dmac@1_stat", ENC(0, 24), 0, input_port, },
987 { "sport@2_stat", ENC(0, 25), 0, input_port, },
988 { "sport@3_stat", ENC(0, 26), 0, input_port, },
989 { "mxvr", ENC(0, 27), 0, input_port, },
990 { "spi@1", ENC(0, 28), 0, input_port, },
991 { "spi@2", ENC(0, 29), 0, input_port, },
992 { "uart2@1_stat", ENC(0, 30), 0, input_port, },
993 { "uart2@2_stat", ENC(0, 31), 0, input_port, },
995 { "can@0_stat", ENC(1, 0), 0, input_port, },
996 { "dma@18", ENC(1, 1), 0, input_port, },
997 { "dma@19", ENC(1, 2), 0, input_port, },
998 { "dma@20", ENC(1, 3), 0, input_port, },
999 { "dma@21", ENC(1, 4), 0, input_port, },
1000 { "dma@13", ENC(1, 5), 0, input_port, },
1001 { "dma@14", ENC(1, 6), 0, input_port, },
1002 { "dma@5", ENC(1, 7), 0, input_port, },
1003 { "dma@23", ENC(1, 8), 0, input_port, },
1004 { "dma@8", ENC(1, 9), 0, input_port, },
1005 { "dma@9", ENC(1, 10), 0, input_port, },
1006 { "dma@10", ENC(1, 11), 0, input_port, },
1007 { "dma@11", ENC(1, 12), 0, input_port, },
1008 { "twi@0", ENC(1, 13), 0, input_port, },
1009 { "twi@1", ENC(1, 14), 0, input_port, },
1010 { "can@0_rx", ENC(1, 15), 0, input_port, },
1011 { "can@0_tx", ENC(1, 16), 0, input_port, },
1012 { "mdma@2", ENC(1, 17), 0, input_port, },
1013 { "mdma@3", ENC(1, 18), 0, input_port, },
1014 { "mxvr_stat", ENC(1, 19), 0, input_port, },
1015 { "mxvr_message", ENC(1, 20), 0, input_port, },
1016 { "mxvr_packet", ENC(1, 21), 0, input_port, },
1017 { "eppi@1", ENC(1, 22), 0, input_port, },
1018 { "eppi@2", ENC(1, 23), 0, input_port, },
1019 { "uart2@3_stat", ENC(1, 24), 0, input_port, },
1020 { "hostdp", ENC(1, 25), 0, input_port, },
1021 /*{ "reserved", ENC(1, 26), 0, input_port, },*/
1022 { "pixc_stat", ENC(1, 27), 0, input_port, },
1023 { "nfc", ENC(1, 28), 0, input_port, },
1024 { "atapi", ENC(1, 29), 0, input_port, },
1025 { "can@1_stat", ENC(1, 30), 0, input_port, },
1026 { "dmar", ENC(1, 31), 0, input_port, },
1028 { "dma@15", ENC(2, 0), 0, input_port, },
1029 { "dma@16", ENC(2, 1), 0, input_port, },
1030 { "dma@17", ENC(2, 2), 0, input_port, },
1031 { "dma@22", ENC(2, 3), 0, input_port, },
1032 { "counter", ENC(2, 4), 0, input_port, },
1033 { "key", ENC(2, 5), 0, input_port, },
1034 { "can@1_rx", ENC(2, 6), 0, input_port, },
1035 { "can@1_tx", ENC(2, 7), 0, input_port, },
1036 { "sdh_mask0", ENC(2, 8), 0, input_port, },
1037 { "sdh_mask1", ENC(2, 9), 0, input_port, },
1038 /*{ "reserved", ENC(2, 10), 0, input_port, },*/
1039 { "usb_int0", ENC(2, 11), 0, input_port, },
1040 { "usb_int1", ENC(2, 12), 0, input_port, },
1041 { "usb_int2", ENC(2, 13), 0, input_port, },
1042 { "usb_dma", ENC(2, 14), 0, input_port, },
1043 { "otpsec", ENC(2, 15), 0, input_port, },
1044 /*{ "reserved", ENC(2, 16), 0, input_port, },*/
1045 /*{ "reserved", ENC(2, 17), 0, input_port, },*/
1046 /*{ "reserved", ENC(2, 18), 0, input_port, },*/
1047 /*{ "reserved", ENC(2, 19), 0, input_port, },*/
1048 /*{ "reserved", ENC(2, 20), 0, input_port, },*/
1049 /*{ "reserved", ENC(2, 21), 0, input_port, },*/
1050 { "gptimer@0", ENC(2, 22), 0, input_port, },
1051 { "gptimer@1", ENC(2, 23), 0, input_port, },
1052 { "gptimer@2", ENC(2, 24), 0, input_port, },
1053 { "gptimer@3", ENC(2, 25), 0, input_port, },
1054 { "gptimer@4", ENC(2, 26), 0, input_port, },
1055 { "gptimer@5", ENC(2, 27), 0, input_port, },
1056 { "gptimer@6", ENC(2, 28), 0, input_port, },
1057 { "gptimer@7", ENC(2, 29), 0, input_port, },
1058 { "pint2", ENC(2, 30), 0, input_port, },
1059 { "pint3", ENC(2, 31), 0, input_port, },
1099 { "pll", ENC(0, 0), 0, input_port, },
1100 { "dmac@0_stat", ENC(0, 1), 0, input_port, },
1101 { "dmac@1_stat", ENC(0, 2), 0, input_port, },
1102 { "imdma_stat", ENC(0, 3), 0, input_port, },
1103 { "ppi@0", ENC(0, 4), 0, input_port, },
1104 { "ppi@1", ENC(0, 5), 0, input_port, },
1105 { "sport@0_stat", ENC(0, 6), 0, input_port, },
1106 { "sport@1_stat", ENC(0, 7), 0, input_port, },
1107 { "spi@0", ENC(0, 8), 0, input_port, },
1108 { "uart@0_stat", ENC(0, 9), 0, input_port, },
1109 /*{ "reserved", ENC(0, 10), 0, input_port, },*/
1110 { "dma@12", ENC(0, 11), 0, input_port, },
1111 { "dma@13", ENC(0, 12), 0, input_port, },
1112 { "dma@14", ENC(0, 13), 0, input_port, },
1113 { "dma@15", ENC(0, 14), 0, input_port, },
1114 { "dma@16", ENC(0, 15), 0, input_port, },
1115 { "dma@17", ENC(0, 16), 0, input_port, },
1116 { "dma@18", ENC(0, 17), 0, input_port, },
1117 { "dma@19", ENC(0, 18), 0, input_port, },
1118 { "dma@20", ENC(0, 19), 0, input_port, },
1119 { "dma@21", ENC(0, 20), 0, input_port, },
1120 { "dma@22", ENC(0, 21), 0, input_port, },
1121 { "dma@23", ENC(0, 22), 0, input_port, },
1122 { "dma@0", ENC(0, 23), 0, input_port, },
1123 { "dma@1", ENC(0, 24), 0, input_port, },
1124 { "dma@2", ENC(0, 25), 0, input_port, },
1125 { "dma@3", ENC(0, 26), 0, input_port, },
1126 { "dma@4", ENC(0, 27), 0, input_port, },
1127 { "dma@5", ENC(0, 28), 0, input_port, },
1128 { "dma@6", ENC(0, 29), 0, input_port, },
1129 { "dma@7", ENC(0, 30), 0, input_port, },
1130 { "dma@8", ENC(0, 31), 0, input_port, },
1132 { "dma@9", ENC(1, 0), 0, input_port, },
1133 { "dma@10", ENC(1, 1), 0, input_port, },
1134 { "dma@11", ENC(1, 2), 0, input_port, },
1135 { "gptimer@0", ENC(1, 3), 0, input_port, },
1136 { "gptimer@1", ENC(1, 4), 0, input_port, },
1137 { "gptimer@2", ENC(1, 5), 0, input_port, },
1138 { "gptimer@3", ENC(1, 6), 0, input_port, },
1139 { "gptimer@4", ENC(1, 7), 0, input_port, },
1140 { "gptimer@5", ENC(1, 8), 0, input_port, },
1141 { "gptimer@6", ENC(1, 9), 0, input_port, },
1142 { "gptimer@7", ENC(1, 10), 0, input_port, },
1143 { "gptimer@8", ENC(1, 11), 0, input_port, },
1144 { "gptimer@9", ENC(1, 12), 0, input_port, },
1145 { "gptimer@10", ENC(1, 13), 0, input_port, },
1146 { "gptimer@11", ENC(1, 14), 0, input_port, },
1147 { "portf_irq_a", ENC(1, 15), 0, input_port, },
1148 { "portf_irq_b", ENC(1, 16), 0, input_port, },
1149 { "portg_irq_a", ENC(1, 17), 0, input_port, },
1150 { "portg_irq_b", ENC(1, 18), 0, input_port, },
1151 { "porth_irq_a", ENC(1, 19), 0, input_port, },
1152 { "porth_irq_b", ENC(1, 20), 0, input_port, },
1153 { "mdma@0", ENC(1, 21), 0, input_port, },
1154 { "mdma@1", ENC(1, 22), 0, input_port, },
1155 { "mdma@2", ENC(1, 23), 0, input_port, },
1156 { "mdma@3", ENC(1, 24), 0, input_port, },
1157 { "imdma@0", ENC(1, 25), 0, input_port, },
1158 { "imdma@1", ENC(1, 26), 0, input_port, },
1159 { "wdog", ENC(1, 27), 0, input_port, },
1160 /*{ "reserved", ENC(1, 28), 0, input_port, },*/
1161 /*{ "reserved", ENC(1, 29), 0, input_port, },*/
1162 { "sup_irq_0", ENC(1, 30), 0, input_port, },
1163 { "sup_irq_1", ENC(1, 31), 0, input_port, },
1199 { "pll", ENC(0, 0), 0, input_port, },
1200 { "dma_stat", ENC(0, 1), 0, input_port, },
1201 { "ppi@0", ENC(0, 2), 0, input_port, },
1202 { "sport@0_stat", ENC(0, 3), 0, input_port, },
1203 { "sport@1_stat", ENC(0, 4), 0, input_port, },
1204 { "spi@0", ENC(0, 5), 0, input_port, },
1205 { "spi@1", ENC(0, 6), 0, input_port, },
1206 { "uart@0_stat", ENC(0, 7), 0, input_port, },
1207 { "dma@0", ENC(0, 8), 0, input_port, },
1208 { "dma@1", ENC(0, 9), 0, input_port, },
1209 { "dma@2", ENC(0, 10), 0, input_port, },
1210 { "dma@3", ENC(0, 11), 0, input_port, },
1211 { "dma@4", ENC(0, 12), 0, input_port, },
1212 { "dma@5", ENC(0, 13), 0, input_port, },
1213 { "dma@6", ENC(0, 14), 0, input_port, },
1214 { "dma@7", ENC(0, 15), 0, input_port, },
1215 { "dma@8", ENC(0, 16), 0, input_port, },
1216 { "portf_irq_a", ENC(0, 17), 0, input_port, },
1217 { "portf_irq_b", ENC(0, 18), 0, input_port, },
1218 { "gptimer@0", ENC(0, 19), 0, input_port, },
1219 { "gptimer@1", ENC(0, 20), 0, input_port, },
1220 { "gptimer@2", ENC(0, 21), 0, input_port, },
1221 { "portg_irq_a", ENC(0, 22), 0, input_port, },
1222 { "portg_irq_b", ENC(0, 23), 0, input_port, },
1223 { "twi@0", ENC(0, 24), 0, input_port, },
1225 { "dma@9", ENC(0, 25), 0, input_port, },
1226 { "dma@10", ENC(0, 26), 0, input_port, },
1227 { "dma@11", ENC(0, 27), 0, input_port, },
1228 { "dma@12", ENC(0, 28), 0, input_port, },
1229 /*{ "reserved", ENC(0, 25), 0, input_port, },*/
1230 /*{ "reserved", ENC(0, 26), 0, input_port, },*/
1231 /*{ "reserved", ENC(0, 27), 0, input_port, },*/
1232 /*{ "reserved", ENC(0, 28), 0, input_port, },*/
1233 { "mdma@0", ENC(0, 29), 0, input_port, },
1234 { "mdma@1", ENC(0, 30), 0, input_port, },
1235 { "wdog", ENC(0, 31), 0, input_port, },