sim/bfin/dv-bfin_sic.c

43       bu32 imask1;
53       bu32 imask0, imask1, imask2;
61       bu32 imask0, imask1;
77   [mmr_idx (bf52x.imask1)] = "SIC_IMASK1", "SIC_IAR4", "SIC_IAR5",
139   bfin_sic_forward_interrupts (me, &sic->bf52x.isr1, &sic->bf52x.imask1, &sic->bf52x.iar4);
175     case mmr_offset(bf52x.imask1):
222     case mmr_offset(bf52x.imask1):
350   bfin_sic_forward_interrupts (me, &sic->bf54x.isr1, &sic->bf54x.imask1, &sic->bf54x.iar4);
450   bfin_sic_forward_interrupts (me, &sic->bf561.isr1, &sic->bf561.imask1, &sic->bf561.iar4);
486     case mmr_offset(bf561.imask1):
533     case mmr_offset(bf561.imask1):
1287       sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
1307       sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
1327       sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
1381       sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
1401       sic->bf54x.imask0 = sic->bf54x.imask1 = sic->bf54x.imask2 = 0;
1425       sic->bf561.imask0 = sic->bf561.imask1 = 0;