Lines Matching refs:SET_Z_CLR_NVC
65 #define SET_Z_CLR_NVC M6811_Z_BIT,M6811_NVC_BIT,0
349 { "clr", OP_IND16, 3, 0x7f, 6, 6, SET_Z_CLR_NVC, cpu6811 },
350 { "clr", OP_IX, 2, 0x6f, 6, 6, SET_Z_CLR_NVC, cpu6811 },
351 { "clr", OP_IY | OP_PAGE2, 3, 0x6f, 7, 7, SET_Z_CLR_NVC, cpu6811 },
352 { "clr", OP_IND16, 3, 0x79, 3, 3, SET_Z_CLR_NVC, cpu6812 },
353 { "clr", OP_IDX, 2, 0x69, 2, 2, SET_Z_CLR_NVC, cpu6812 },
354 { "clr", OP_IDX_1, 3, 0x69, 3, 3, SET_Z_CLR_NVC, cpu6812 },
355 { "clr", OP_IDX_2, 4, 0x69, 4, 4, SET_Z_CLR_NVC, cpu6812 },
356 { "clr", OP_D_IDX, 2, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 },
357 { "clr", OP_D_IDX_2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 },
359 { "clra", OP_NONE, 1, 0x4f, 2, 2, SET_Z_CLR_NVC, cpu6811 },
360 { "clrb", OP_NONE, 1, 0x5f, 2, 2, SET_Z_CLR_NVC, cpu6811 },
361 { "clra", OP_NONE, 1, 0x87, 1, 1, SET_Z_CLR_NVC, cpu6812 },
362 { "clrb", OP_NONE, 1, 0xc7, 1, 1, SET_Z_CLR_NVC, cpu6812 },