dist/opcodes/m68hc11-opc.c

86 #define OP_BITMASK      M6811_OP_BITMASK
226   { "bclr", OP_BITMASK|OP_DIRECT,  3, 0x15,  6,  6,  CLR_V_CHG_NZ, cpu6811 },
227   { "bclr", OP_BITMASK|OP_IX,       3, 0x1d,  7,  7,  CLR_V_CHG_NZ, cpu6811 },
228   { "bclr", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811},
229   { "bclr", OP_BITMASK|OP_DIRECT,   3, 0x4d,  4,  4,  CLR_V_CHG_NZ, cpu6812 },
230   { "bclr", OP_BITMASK|OP_IND16,    4, 0x1d,  4,  4,  CLR_V_CHG_NZ, cpu6812 },
231   { "bclr", OP_BITMASK|OP_IDX,      3, 0x0d,  4,  4,  CLR_V_CHG_NZ, cpu6812 },
232   { "bclr", OP_BITMASK|OP_IDX_1,    4, 0x0d,  4,  4,  CLR_V_CHG_NZ, cpu6812 },
233   { "bclr", OP_BITMASK|OP_IDX_2,    5, 0x0d,  6,  6,  CLR_V_CHG_NZ, cpu6812 },
276   { "brclr", OP_BITMASK | OP_JUMP_REL
278   { "brclr", OP_BITMASK | OP_JUMP_REL
280   { "brclr", OP_BITMASK | OP_JUMP_REL
282   { "brclr", OP_BITMASK | OP_JUMP_REL
284   { "brclr", OP_BITMASK | OP_JUMP_REL
286   { "brclr", OP_BITMASK | OP_JUMP_REL
288   { "brclr", OP_BITMASK | OP_JUMP_REL
290   { "brclr", OP_BITMASK
296   { "brset", OP_BITMASK | OP_JUMP_REL
298   { "brset", OP_BITMASK
301   { "brset", OP_BITMASK | OP_JUMP_REL
303   { "brset", OP_BITMASK | OP_JUMP_REL
305   { "brset", OP_BITMASK | OP_JUMP_REL
307   { "brset", OP_BITMASK | OP_JUMP_REL
309   { "brset", OP_BITMASK | OP_JUMP_REL
311   { "brset", OP_BITMASK | OP_JUMP_REL
315   { "bset", OP_BITMASK | OP_DIRECT,   3, 0x14,  6,  6, CLR_V_CHG_NZ, cpu6811 },
316   { "bset", OP_BITMASK | OP_IX,       3, 0x1c,  7,  7, CLR_V_CHG_NZ, cpu6811 },
317   { "bset", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811 },
318   { "bset", OP_BITMASK|OP_DIRECT,   3, 0x4c,  4,  4,  CLR_V_CHG_NZ, cpu6812 },
319   { "bset", OP_BITMASK|OP_IND16,    4, 0x1c,  4,  4,  CLR_V_CHG_NZ, cpu6812 },
320   { "bset", OP_BITMASK|OP_IDX,      3, 0x0c,  4,  4,  CLR_V_CHG_NZ, cpu6812 },
321   { "bset", OP_BITMASK|OP_IDX_1,    4, 0x0c,  4,  4,  CLR_V_CHG_NZ, cpu6812 },
322   { "bset", OP_BITMASK|OP_IDX_2,    5, 0x0c,  6,  6,  CLR_V_CHG_NZ, cpu6812 },