gas/config/tc-arm.c

270    tc_frag_data field of a frag.  */
352   /* "uncond_value" is set to the value in place of the conditional field in
379     unsigned immisreg	: 1;  /* .imm field is a second register.  */
440   unsigned long  field;
475 /* Bits for DEFINED field in neon_typed_alias.  */
515    If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
5200 	      inst.error = _("'}' expected at end of 'option' field");
5351       return psr->field;
5370       psr_field |= psr->field;
5388    value suitable for splatting into the AIF field of the instruction.	*/
5453    value suitable for poking into the rotate field of an sxt or sxta
5466       inst.error = _("missing rotation field after comma");
5597    ".present" field for each read operand itself.
6664 /* If VAL can be encoded in the immediate field of an ARM instruction,
6679 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7225   constraint (msb > 32, _("bit-field extends past end of register"));
7239      the same instruction but with REG_PC in the Rm field.  */
7244   constraint (msb > 32, _("bit-field extends past end of register"));
7257 	      _("bit-field extends past end of register"));
7892       "{C|S}PSR_<field>, Rm",
9579   constraint (msb > 32, _("bit-field extends past end of register"));
9600      the same instruction but with REG_PC in the Rm field.  */
9610   constraint (msb > 32, _("bit-field extends past end of register"));
9632 	      _("bit-field extends past end of register"));
12467 /* Thumb VFP instructions have 0xE in the condition field.  */
12838   SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13080    the instruction. *OP is passed as the initial value of the op field, and
13248       /* U bit and size field were set as part of the bitmask.  */
13389      - Alter the value in the condition code field if necessary.
13396    current instruction's condition is COND_ALWAYS, the condition field is
13399    unconditional Neon version must have, e.g., 0xF in the condition field.  */
13662   /* Size field comes from bit mask.  */
14371       /* For polynomial encoding, size field must be 0b00 and the U bit must be
14462          variants, except for the condition field.  */
14789   /* Unsigned is encoded in OP field (bit 7) for these instruction.  */
15395 /* Tag values used in struct asm_opcode's tag field.  */
15399 			   The ARM condition field is still 0xE.  */
15401 			   and carries 0xF in its ARM condition field.  */
15404                            suffix, others place 0xF where the condition field
15464    U. Examine the tag field of the opcode structure, in case this is
15471   CE. Examine the tag field to make sure this is an instruction that
15476   CM. Examine the tag field to make sure this is an instruction that
15985      condition field.  */
16663    field is still 0xE.  Many of the Thumb variants can be executed
16670    condition code field.  */
18854 	 This doesn't handle the fr_subtype field, which specifies
18921    size of the offset field in the narrow instruction.  */
20634 	 instruction, in a 24 bit, signed field.  Bits 26 through 32 either
21022 	 instruction field: