Lines Matching defs:SrcReg
1345 unsigned &SrcReg, unsigned &DstReg,
1368 SrcReg = MI.getOperand(1).getReg();
2758 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2760 // SrcReg(VR128) -> DestReg(GR64)
2761 // SrcReg(VR64) -> DestReg(GR64)
2762 // SrcReg(GR64) -> DestReg(VR128)
2763 // SrcReg(GR64) -> DestReg(VR64)
2766 if (X86::VR128RegClass.contains(SrcReg))
2769 if (X86::VR64RegClass.contains(SrcReg))
2772 } else if (X86::GR64RegClass.contains(SrcReg)) {
2781 // SrcReg(FR32) -> DestReg(GR32)
2782 // SrcReg(GR32) -> DestReg(FR32)
2784 if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
2788 if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
2797 unsigned DestReg, unsigned SrcReg,
2802 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2804 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2806 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2808 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2811 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2815 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2819 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2821 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2823 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2826 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
2830 .addReg(SrcReg, getKillRegState(KillSrc));
2835 if (SrcReg == X86::EFLAGS) {
2848 if (X86::GR64RegClass.contains(SrcReg)) {
2850 .addReg(SrcReg, getKillRegState(KillSrc));
2854 if (X86::GR32RegClass.contains(SrcReg)) {
2856 .addReg(SrcReg, getKillRegState(KillSrc));
2862 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2934 static unsigned getStoreRegOpcode(unsigned SrcReg,
2938 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2951 unsigned SrcReg, bool isKill, int FrameIdx,
2960 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2963 .addReg(SrcReg, getKillRegState(isKill));
2966 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2976 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2981 MIB.addReg(SrcReg, getKillRegState(isKill));
3020 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3031 SrcReg = MI->getOperand(0).getReg();
3041 SrcReg = MI->getOperand(1).getReg();
3050 SrcReg = MI->getOperand(1).getReg();
3062 SrcReg = MI->getOperand(1).getReg();
3071 SrcReg = MI->getOperand(0).getReg();
3080 SrcReg = MI->getOperand(0).getReg();
3081 if (MI->getOperand(1).getReg() != SrcReg) return false;
3095 /// SrcReg, SrcRegs: register operands for FlagI.
3097 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3108 ((OI->getOperand(1).getReg() == SrcReg &&
3111 OI->getOperand(2).getReg() == SrcReg)))
3128 OI->getOperand(1).getReg() == SrcReg &&
3180 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3232 // Get the unique definition of SrcReg.
3233 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3266 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
3297 Sub->getOperand(2).getReg() == SrcReg);