Lines Matching defs:VA
1522 CCValAssign &VA = RVLocs[i];
1523 assert(VA.isRegLoc() && "Can only return in registers!");
1528 if (VA.getLocInfo() == CCValAssign::SExt)
1529 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1530 else if (VA.getLocInfo() == CCValAssign::ZExt)
1531 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1532 else if (VA.getLocInfo() == CCValAssign::AExt)
1533 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1534 else if (VA.getLocInfo() == CCValAssign::BCvt)
1535 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1540 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1553 if (VA.getLocReg() == X86::ST0 ||
1554 VA.getLocReg() == X86::ST1) {
1557 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1568 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1580 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1679 CCValAssign &VA = RVLocs[i];
1680 EVT CopyVT = VA.getValVT();
1695 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1698 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1706 if (CopyVT != VA.getValVT())
1707 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1711 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1813 const CCValAssign &VA,
1825 if (VA.getLocInfo() == CCValAssign::Indirect)
1826 ValVT = VA.getLocVT();
1828 ValVT = VA.getValVT();
1837 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1841 VA.getLocMemOffset(), isImmutable);
1890 CCValAssign &VA = ArgLocs[i];
1893 assert(VA.getValNo() != LastVal &&
1896 LastVal = VA.getValNo();
1898 if (VA.isRegLoc()) {
1899 EVT RegVT = VA.getLocVT();
1918 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1924 if (VA.getLocInfo() == CCValAssign::SExt)
1926 DAG.getValueType(VA.getValVT()));
1927 else if (VA.getLocInfo() == CCValAssign::ZExt)
1929 DAG.getValueType(VA.getValVT()));
1930 else if (VA.getLocInfo() == CCValAssign::BCvt)
1931 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1933 if (VA.isExtInLoc()) {
1936 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1939 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1942 assert(VA.isMemLoc());
1943 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1947 if (VA.getLocInfo() == CCValAssign::Indirect)
1948 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2128 const CCValAssign &VA,
2130 unsigned LocMemOffset = VA.getLocMemOffset();
2272 CCValAssign &VA = ArgLocs[i];
2273 EVT RegVT = VA.getLocVT();
2279 switch (VA.getLocInfo()) {
2302 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2312 if (VA.isRegLoc()) {
2313 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2318 switch (VA.getLocReg()) {
2328 assert(VA.isMemLoc());
2332 dl, DAG, VA, Flags));
2402 CCValAssign &VA = ArgLocs[i];
2403 if (VA.isRegLoc())
2405 assert(VA.isMemLoc());
2409 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2410 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2416 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2807 CCValAssign &VA = RVLocs[i];
2808 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2870 CCValAssign &VA = ArgLocs[i];
2873 if (VA.getLocInfo() == CCValAssign::Indirect)
2875 if (!VA.isRegLoc()) {
2876 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2893 CCValAssign &VA = ArgLocs[i];
2894 if (!VA.isRegLoc())
2896 unsigned Reg = VA.getLocReg();