Lines Matching refs:V0
128 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
138 V0 = RegInfo.createVirtualRegister(RC);
150 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
152 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
160 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
164 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
175 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
177 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
190 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
192 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
214 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
217 MF.getRegInfo().addLiveIn(Mips::V0);
218 MBB.addLiveIn(Mips::V0);
220 .addReg(Mips::V0).addReg(Mips::T9);