Lines Matching refs:V0
269 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
270 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
271 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
274 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
275 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
276 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1449 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1450 DebugLoc dl = V0.getNode()->getDebugLoc();
1455 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1461 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1462 DebugLoc dl = V0.getNode()->getDebugLoc();
1466 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1472 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1473 DebugLoc dl = V0.getNode()->getDebugLoc();
1477 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1483 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1485 DebugLoc dl = V0.getNode()->getDebugLoc();
1492 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1499 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1501 DebugLoc dl = V0.getNode()->getDebugLoc();
1507 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1514 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1516 DebugLoc dl = V0.getNode()->getDebugLoc();
1522 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1784 SDValue V0 = N->getOperand(Vec0Idx + 0);
1787 SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1795 SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1837 SDValue V0 = N->getOperand(Vec0Idx + 0);
1843 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1949 SDValue V0 = N->getOperand(Vec0Idx + 0);
1953 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1955 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1962 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1964 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
2087 SDValue V0 = N->getOperand(FirstTblReg + 0);
2090 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
2098 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
3296 SDValue V0 = N->getOperand(0);
3298 SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);