Lines Matching refs:isSigned
96 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
98 unsigned NumOps, bool isSigned, DebugLoc dl);
101 SDNode *Node, bool isSigned);
105 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
119 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
121 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
123 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
1847 bool isSigned) {
1854 Entry.isSExt = isSigned;
1855 Entry.isZExt = !isSigned;
1877 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1895 bool isSigned, DebugLoc dl) {
1903 Entry.isSExt = isSigned;
1904 Entry.isZExt = !isSigned;
1912 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1927 bool isSigned) {
1937 Entry.isSExt = isSigned;
1938 Entry.isZExt = !isSigned;
1946 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1971 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1986 return ExpandLibCall(LC, Node, isSigned);
1990 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
1995 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
1996 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
1997 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
1998 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
1999 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2007 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2009 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2011 if (isSigned)
2037 bool isSigned = Opcode == ISD::SDIVREM;
2042 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2043 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2044 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2045 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2046 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2063 Entry.isSExt = isSigned;
2064 Entry.isZExt = !isSigned;
2072 Entry.isSExt = isSigned;
2073 Entry.isZExt = !isSigned;
2081 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2098 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2119 if (isSigned) {
2140 SDValue Bias = DAG.getConstantFP(isSigned ?
2160 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2161 // Code below here assumes !isSigned without checking again.
2193 if (!isSigned) {
2299 bool isSigned,
2316 if (isSigned) continue;
2330 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2341 bool isSigned,
3162 bool isSigned = Node->getOpcode() == ISD::SREM;
3163 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3164 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3168 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3171 useDivRem(Node, isSigned, false))) {
3178 } else if (isSigned)
3193 bool isSigned = Node->getOpcode() == ISD::SDIV;
3194 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3198 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3199 useDivRem(Node, isSigned, true)))
3202 else if (isSigned)
3325 bool isSigned = Node->getOpcode() == ISD::SMULO;
3326 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3328 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3329 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3330 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3335 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3336 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3371 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3382 if (isSigned) {