Lines Matching defs:VReg
271 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
274 if (!VReg) {
276 VReg = MRI->createVirtualRegister(RC);
279 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
280 return VReg;
302 unsigned VReg = getVR(Op, VRBaseMap);
303 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
311 // shrink VReg's register class within reason. For example, if VReg == GR32
312 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
317 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
320 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
321 VReg = NewVReg;
346 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
428 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
430 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
433 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
436 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
438 // VReg has been adjusted. It can be used with SubIdx operands now.
440 return VReg;
442 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
448 .addReg(VReg);
482 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
483 MachineInstr *DefMI = MRI->getVRegDef(VReg);
499 // VReg may not support a SubIdx sub-register, and we may need to
502 VReg = ConstrainForSubReg(VReg, SubIdx,
512 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
575 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
577 // Create the new VReg in the destination class and emit a copy.
583 NewVReg).addReg(VReg);