Lines Matching refs:cc
271 void bitAnd(int rd, int rn, ARMWord op2, Condition cc = AL)
273 emitInstruction(toARMWord(cc) | AND, rd, rn, op2);
276 void bitAnds(int rd, int rn, ARMWord op2, Condition cc = AL)
278 emitInstruction(toARMWord(cc) | AND | SetConditionalCodes, rd, rn, op2);
281 void eor(int rd, int rn, ARMWord op2, Condition cc = AL)
283 emitInstruction(toARMWord(cc) | EOR, rd, rn, op2);
286 void eors(int rd, int rn, ARMWord op2, Condition cc = AL)
288 emitInstruction(toARMWord(cc) | EOR | SetConditionalCodes, rd, rn, op2);
291 void sub(int rd, int rn, ARMWord op2, Condition cc = AL)
293 emitInstruction(toARMWord(cc) | SUB, rd, rn, op2);
296 void subs(int rd, int rn, ARMWord op2, Condition cc = AL)
298 emitInstruction(toARMWord(cc) | SUB | SetConditionalCodes, rd, rn, op2);
301 void rsb(int rd, int rn, ARMWord op2, Condition cc = AL)
303 emitInstruction(toARMWord(cc) | RSB, rd, rn, op2);
306 void rsbs(int rd, int rn, ARMWord op2, Condition cc = AL)
308 emitInstruction(toARMWord(cc) | RSB | SetConditionalCodes, rd, rn, op2);
311 void add(int rd, int rn, ARMWord op2, Condition cc = AL)
313 emitInstruction(toARMWord(cc) | ADD, rd, rn, op2);
316 void adds(int rd, int rn, ARMWord op2, Condition cc = AL)
318 emitInstruction(toARMWord(cc) | ADD | SetConditionalCodes, rd, rn, op2);
321 void adc(int rd, int rn, ARMWord op2, Condition cc = AL)
323 emitInstruction(toARMWord(cc) | ADC, rd, rn, op2);
326 void adcs(int rd, int rn, ARMWord op2, Condition cc = AL)
328 emitInstruction(toARMWord(cc) | ADC | SetConditionalCodes, rd, rn, op2);
331 void sbc(int rd, int rn, ARMWord op2, Condition cc = AL)
333 emitInstruction(toARMWord(cc) | SBC, rd, rn, op2);
336 void sbcs(int rd, int rn, ARMWord op2, Condition cc = AL)
338 emitInstruction(toARMWord(cc) | SBC | SetConditionalCodes, rd, rn, op2);
341 void rsc(int rd, int rn, ARMWord op2, Condition cc = AL)
343 emitInstruction(toARMWord(cc) | RSC, rd, rn, op2);
346 void rscs(int rd, int rn, ARMWord op2, Condition cc = AL)
348 emitInstruction(toARMWord(cc) | RSC | SetConditionalCodes, rd, rn, op2);
351 void tst(int rn, ARMWord op2, Condition cc = AL)
353 emitInstruction(toARMWord(cc) | TST | SetConditionalCodes, 0, rn, op2);
356 void teq(int rn, ARMWord op2, Condition cc = AL)
358 emitInstruction(toARMWord(cc) | TEQ | SetConditionalCodes, 0, rn, op2);
361 void cmp(int rn, ARMWord op2, Condition cc = AL)
363 emitInstruction(toARMWord(cc) | CMP | SetConditionalCodes, 0, rn, op2);
366 void cmn(int rn, ARMWord op2, Condition cc = AL)
368 emitInstruction(toARMWord(cc) | CMN | SetConditionalCodes, 0, rn, op2);
371 void orr(int rd, int rn, ARMWord op2, Condition cc = AL)
373 emitInstruction(toARMWord(cc) | ORR, rd, rn, op2);
376 void orrs(int rd, int rn, ARMWord op2, Condition cc = AL)
378 emitInstruction(toARMWord(cc) | ORR | SetConditionalCodes, rd, rn, op2);
381 void mov(int rd, ARMWord op2, Condition cc = AL)
383 emitInstruction(toARMWord(cc) | MOV, rd, ARMRegisters::r0, op2);
387 void movw(int rd, ARMWord op2, Condition cc = AL)
390 m_buffer.putInt(toARMWord(cc) | MOVW | RD(rd) | op2);
393 void movt(int rd, ARMWord op2, Condition cc = AL)
396 m_buffer.putInt(toARMWord(cc) | MOVT | RD(rd) | op2);
400 void movs(int rd, ARMWord op2, Condition cc = AL)
402 emitInstruction(toARMWord(cc) | MOV | SetConditionalCodes, rd, ARMRegisters::r0, op2);
405 void bic(int rd, int rn, ARMWord op2, Condition cc = AL)
407 emitInstruction(toARMWord(cc) | BIC, rd, rn, op2);
410 void bics(int rd, int rn, ARMWord op2, Condition cc = AL)
412 emitInstruction(toARMWord(cc) | BIC | SetConditionalCodes, rd, rn, op2);
415 void mvn(int rd, ARMWord op2, Condition cc = AL)
417 emitInstruction(toARMWord(cc) | MVN, rd, ARMRegisters::r0, op2);
420 void mvns(int rd, ARMWord op2, Condition cc = AL)
422 emitInstruction(toARMWord(cc) | MVN | SetConditionalCodes, rd, ARMRegisters::r0, op2);
425 void mul(int rd, int rn, int rm, Condition cc = AL)
427 m_buffer.putInt(toARMWord(cc) | MUL | RN(rd) | RS(rn) | RM(rm));
430 void muls(int rd, int rn, int rm, Condition cc = AL)
432 m_buffer.putInt(toARMWord(cc) | MUL | SetConditionalCodes | RN(rd) | RS(rn) | RM(rm));
435 void mull(int rdhi, int rdlo, int rn, int rm, Condition cc = AL)
437 m_buffer.putInt(toARMWord(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm));
440 void vmov_f64(int dd, int dm, Condition cc = AL)
442 emitDoublePrecisionInstruction(toARMWord(cc) | VMOV_F64, dd, 0, dm);
445 void vadd_f64(int dd, int dn, int dm, Condition cc = AL)
447 emitDoublePrecisionInstruction(toARMWord(cc) | VADD_F64, dd, dn, dm);
450 void vdiv_f64(int dd, int dn, int dm, Condition cc = AL)
452 emitDoublePrecisionInstruction(toARMWord(cc) | VDIV_F64, dd, dn, dm);
455 void vsub_f64(int dd, int dn, int dm, Condition cc = AL)
457 emitDoublePrecisionInstruction(toARMWord(cc) | VSUB_F64, dd, dn, dm);
460 void vmul_f64(int dd, int dn, int dm, Condition cc = AL)
462 emitDoublePrecisionInstruction(toARMWord(cc) | VMUL_F64, dd, dn, dm);
465 void vcmp_f64(int dd, int dm, Condition cc = AL)
467 emitDoublePrecisionInstruction(toARMWord(cc) | VCMP_F64, dd, 0, dm);
470 void vsqrt_f64(int dd, int dm, Condition cc = AL)
472 emitDoublePrecisionInstruction(toARMWord(cc) | VSQRT_F64, dd, 0, dm);
475 void vabs_f64(int dd, int dm, Condition cc = AL)
477 emitDoublePrecisionInstruction(toARMWord(cc) | VABS_F64, dd, 0, dm);
480 void vneg_f64(int dd, int dm, Condition cc = AL)
482 emitDoublePrecisionInstruction(toARMWord(cc) | VNEG_F64, dd, 0, dm);
485 void ldrImmediate(int rd, ARMWord imm, Condition cc = AL)
487 m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm, true);
490 void ldrUniqueImmediate(int rd, ARMWord imm, Condition cc = AL)
492 m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm);
495 void dtrUp(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
497 emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
500 void dtrUpRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
502 emitInstruction(toARMWord(cc) | transferType | DataTransferUp | Op2IsRegisterArgument, rd, rb, rm);
505 void dtrDown(DataTransferTypeA transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
507 emitInstruction(toARMWord(cc) | transferType, rd, rb, op2);
510 void dtrDownRegister(DataTransferTypeA transferType, int rd, int rb, int rm, Condition cc = AL)
512 emitInstruction(toARMWord(cc) | transferType | Op2IsRegisterArgument, rd, rb, rm);
515 void halfDtrUp(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
517 emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rb, op2);
520 void halfDtrUpRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
522 emitInstruction(toARMWord(cc) | transferType | DataTransferUp, rd, rn, rm);
525 void halfDtrDown(DataTransferTypeB transferType, int rd, int rb, ARMWord op2, Condition cc = AL)
527 emitInstruction(toARMWord(cc) | transferType, rd, rb, op2);
530 void halfDtrDownRegister(DataTransferTypeB transferType, int rd, int rn, int rm, Condition cc = AL)
532 emitInstruction(toARMWord(cc) | transferType, rd, rn, rm);
535 void doubleDtrUp(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
539 m_buffer.putInt(toARMWord(cc) | DataTransferUp | type | (rd << 12) | RN(rb) | op2);
542 void doubleDtrDown(DataTransferTypeFloat type, int rd, int rb, ARMWord op2, Condition cc = AL)
546 m_buffer.putInt(toARMWord(cc) | type | (rd << 12) | RN(rb) | op2);
549 void push(int reg, Condition cc = AL)
552 m_buffer.putInt(toARMWord(cc) | StoreUint32 | DataTransferWriteBack | RN(ARMRegisters::sp) | RD(reg) | 0x4);
555 void pop(int reg, Condition cc = AL)
558 m_buffer.putInt(toARMWord(cc) | (LoadUint32 ^ DataTransferPostUpdate) | DataTransferUp | RN(ARMRegisters::sp) | RD(reg) | 0x4);
561 inline void poke(int reg, Condition cc = AL)
563 dtrDown(StoreUint32, ARMRegisters::sp, 0, reg, cc);
566 inline void peek(int reg, Condition cc = AL)
568 dtrUp(LoadUint32, reg, ARMRegisters::sp, 0, cc);
571 void vmov_vfp64(int sm, int rt, int rt2, Condition cc = AL)
574 m_buffer.putInt(toARMWord(cc) | VMOV_VFP64 | RN(rt2) | RD(rt) | (sm & 0xf) | ((sm & 0x10) << (5 - 4)));
577 void vmov_arm64(int rt, int rt2, int sm, Condition cc = AL)
580 m_buffer.putInt(toARMWord(cc) | VMOV_ARM64 | RN(rt2) | RD(rt) | (sm & 0xf) | ((sm & 0x10) << (5 - 4)));
583 void vmov_vfp32(int sn, int rt, Condition cc = AL)
586 emitSinglePrecisionInstruction(toARMWord(cc) | VMOV_VFP32, rt << 1, sn, 0);
589 void vmov_arm32(int rt, int sn, Condition cc = AL)
592 emitSinglePrecisionInstruction(toARMWord(cc) | VMOV_ARM32, rt << 1, sn, 0);
595 void vcvt_f64_s32(int dd, int sm, Condition cc = AL)
598 emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F64_S32, dd, 0, (sm >> 1));
601 void vcvt_s32_f64(int sd, int dm, Condition cc = AL)
604 emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_S32_F64, (sd >> 1), 0, dm);
607 void vcvt_u32_f64(int sd, int dm, Condition cc = AL)
610 emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_U32_F64, (sd >> 1), 0, dm);
613 void vcvt_f64_f32(int dd, int sm, Condition cc = AL)
616 emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F64_F32, dd, 0, sm);
619 void vcvt_f32_f64(int dd, int sm, Condition cc = AL)
622 emitDoublePrecisionInstruction(toARMWord(cc) | VCVT_F32_F64, dd, 0, sm);
625 void vmrs_apsr(Condition cc = AL)
627 m_buffer.putInt(toARMWord(cc) | VMRS_APSR);
630 void clz(int rd, int rm, Condition cc = AL)
632 m_buffer.putInt(toARMWord(cc) | CLZ | RD(rd) | RM(rm));
645 void bx(int rm, Condition cc = AL)
647 emitInstruction(toARMWord(cc) | BX, 0, 0, RM(rm));
650 AssemblerLabel blx(int rm, Condition cc = AL)
652 emitInstruction(toARMWord(cc) | BLX, 0, 0, RM(rm));
750 AssemblerLabel loadBranchTarget(int rd, Condition cc = AL, int useConstantPool = 0)
754 ldrUniqueImmediate(rd, InvalidBranchTarget, cc);
758 AssemblerLabel jmp(Condition cc = AL, int useConstantPool = 0)
760 return loadBranchTarget(ARMRegisters::pc, cc, useConstantPool);
1108 static ARMWord toARMWord(Condition cc)
1110 return static_cast<ARMWord>(cc);