Lines Matching refs:sr
496 struct scc_softreg *sr;
508 sr = &scc->softr[chan];
511 if ((sr->flags & (TF_ODDP|TF_EVENP)) == (tp->t_flags & (TF_ODDP|TF_EVENP))
512 && sr->speed == (unsigned long)tp->t_ispeed) {
522 sr->wr1 = SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_EXT_IE;
523 scc_write_reg(regs, chan, 1, sr->wr1);
531 sr->wr1 = SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_EXT_IE;
532 scc_write_reg(regs, chan, 1, sr->wr1);
539 sr->flags = tp->t_flags;
540 sr->speed = tp->t_ispeed;
544 sr->wr5 &= ~SCC_WR5_DTR;
545 scc_write_reg(regs, chan, 5, sr->wr5);
581 sr->wr4 = value;
584 scc_write_reg(regs, chan, 4, sr->wr4);
590 sr->wr5 = SCC_WR5_TX_8_BITS | SCC_WR5_RTS | SCC_WR5_DTR;
592 scc_write_reg(regs, chan, 5, sr->wr5);
620 sr->wr1 = SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_EXT_IE;
621 scc_write_reg(regs, chan, 1, sr->wr1);
644 sr->wr1 = SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_EXT_IE;
645 scc_write_reg(regs, chan, 1, sr->wr1);
649 sr->wr5 |= SCC_WR5_TX_ENABLE;
650 scc_write_reg(regs, chan, 5, sr->wr5);