Lines Matching defs:chan
99 #define scc_tty_for(chan) (&scc_tty[chan])
102 #define scc_dev_no(chan) ((chan)^0x01)
198 int i, chan, bits;
225 for (chan = 0; chan < NSCC_LINE; chan++) {
226 if (chan == 1)
230 scc_write_reg(regs, chan,
494 int bits, chan;
504 chan = scc_chan(tp->t_dev);
508 sr = &scc->softr[chan];
521 scc_write_reg(regs, chan, 3, SCC_WR3_RX_8_BITS|SCC_WR3_RX_ENABLE);
523 scc_write_reg(regs, chan, 1, sr->wr1);
524 scc_write_reg(regs, chan, 15, SCC_WR15_ENABLE_ESCC);
525 scc_write_reg(regs, chan, 7, SCC_WR7P_RX_FIFO);
526 scc_write_reg(regs, chan, 0, SCC_IE_NEXT_CHAR);
527 scc_write_reg(regs, chan, 0, SCC_RESET_EXT_IP);
528 scc_write_reg(regs, chan, 0, SCC_RESET_EXT_IP);
529 scc_write_reg(regs, chan, 9, SCC_WR9_MASTER_IE|SCC_WR9_NV);
532 scc_write_reg(regs, chan, 1, sr->wr1);
533 scc_write_reg(regs, chan, 0, SCC_IE_NEXT_CHAR);
545 scc_write_reg(regs, chan, 5, sr->wr5);
555 if (scc->dma_initted & (1<<chan))
556 scc->dma_ops->scc_dma_reset_rx(chan);
584 scc_write_reg(regs, chan, 4, sr->wr4);
587 scc_write_reg(regs, chan, 3, SCC_WR3_RX_8_BITS);
592 scc_write_reg(regs, chan, 5, sr->wr5);
594 scc_write_reg(regs, chan, 14, 0); /* Disable baud rate */
604 scc_set_timing_base(regs, chan, speed_value);
608 scc_write_reg(regs, chan, 11, 0);
611 scc_write_reg(regs, chan, 11, SCC_WR11_RCLK_BAUDR|SCC_WR11_XTLK_BAUDR);
613 scc_write_reg(regs, chan, 14, SCC_WR14_BAUDR_ENABLE);
617 scc_write_reg(regs, chan, 3, SCC_WR3_RX_8_BITS|SCC_WR3_RX_ENABLE);
621 scc_write_reg(regs, chan, 1, sr->wr1);
622 scc_write_reg(regs, chan, 15, SCC_WR15_ENABLE_ESCC);
623 scc_write_reg(regs, chan, 7, SCC_WR7P_RX_FIFO);
624 scc_write_reg(regs, chan, 0, SCC_IE_NEXT_CHAR);
628 scc_write_reg(regs, chan, 0, SCC_RESET_EXT_IP);
629 scc_write_reg(regs, chan, 0, SCC_RESET_EXT_IP);
630 //scc_write_reg(regs, chan, 0, SCC_RESET_ERROR);
633 scc_write_reg(regs, chan, 9, SCC_WR9_MASTER_IE|SCC_WR9_NV);
638 if (scc->dma_initted & (1<<chan)) {
639 scc->dma_ops->scc_dma_start_rx(chan);
640 scc->dma_ops->scc_dma_setup_8530(chan);
645 scc_write_reg(regs, chan, 1, sr->wr1);
646 scc_write_reg(regs, chan, 0, SCC_IE_NEXT_CHAR);
650 scc_write_reg(regs, chan, 5, sr->wr5);