Lines Matching defs:proc_info
235 struct per_proc_info *proc_info;
239 proc_info = getPerProc();
241 proc_info->interrupt_nub = nub;
242 proc_info->interrupt_source = source;
243 proc_info->interrupt_target = target;
244 proc_info->interrupt_handler = handler;
245 proc_info->interrupt_refCon = refCon;
247 proc_info->interrupts_enabled = TRUE;
370 struct per_proc_info *proc_info;
372 proc_info = PROCESSOR_TO_PER_PROC(processor);
374 if (proc_info->pf.Available & (pfCanDoze|pfWillNap))
375 (void)cpu_signal(proc_info->cpu_number, SIGPwake, 0, 0);
388 struct per_proc_info *proc_info;
399 proc_info = cpu_per_proc_alloc();
400 if (proc_info == (struct per_proc_info *)NULL)
402 proc_info->pp_cbfr = console_per_proc_alloc(FALSE);
403 if (proc_info->pp_cbfr == (void *)NULL)
407 proc_info = PerProcTable[master_cpu].ppe_vaddr;
410 proc_info->pp_chud = chudxnu_per_proc_alloc(boot_processor);
411 if (proc_info->pp_chud == (void *)NULL)
415 if (cpu_per_proc_register(proc_info) != KERN_SUCCESS)
418 proc_info->cpu_id = in_processor_info->cpu_id;
419 proc_info->start_paddr = in_processor_info->start_paddr;
421 proc_info->time_base_enable = in_processor_info->time_base_enable;
423 proc_info->time_base_enable = (void(*)(cpu_id_t, boolean_t ))NULL;
425 if((proc_info->pf.pfPowerModes & pmType) == pmPowerTune) {
426 proc_info->pf.pfPowerTune0 = in_processor_info->power_mode_0;
427 proc_info->pf.pfPowerTune1 = in_processor_info->power_mode_1;
433 if((proc_info->pf.Available & pfCanNap)
435 proc_info->pf.Available |= pfWillNap;
437 if(proc_info == getPerProc())
438 __asm__ volatile("mtsprg 2,%0" : : "r" (proc_info->pf.Available)); /* Set live value */
444 processor_init((struct processor *)proc_info->processor,
445 proc_info->cpu_number, processor_pset(master_processor));
448 *processor_out = (struct processor *)proc_info->processor;
454 if (proc_info->pp_cbfr != (void *)NULL)
455 console_per_proc_free(proc_info->pp_cbfr);
456 if (proc_info->pp_chud != (void *)NULL)
457 chudxnu_per_proc_free(proc_info->pp_chud);
459 cpu_per_proc_free(proc_info);
470 struct per_proc_info *proc_info;
474 proc_info = PerProcTable[target_cpu].ppe_vaddr;
476 prev_value = (proc_info->pf.Available & pfCanNap) && (proc_info->pf.Available & pfWillNap);
480 if(proc_info->pf.Available & pfCanNap) { /* Can the processor nap? */
481 if (nap_enabled) proc_info->pf.Available |= pfWillNap; /* Is nap supported on this machine? */
482 else proc_info->pf.Available &= ~pfWillNap; /* Clear if not */
486 if(proc_info == getPerProc())
487 __asm__ volatile("mtsprg 2,%0" : : "r" (proc_info->pf.Available)); /* Set live value */
588 struct per_proc_info *proc_info;
592 proc_info = PerProcTable[master_cpu].ppe_vaddr;
593 ml_cpu_info->vector_unit = (proc_info->pf.Available & pfAltivec) != 0;
594 ml_cpu_info->cache_line_size = proc_info->pf.lineSize;
595 ml_cpu_info->l1_icache_size = proc_info->pf.l1iSize;
596 ml_cpu_info->l1_dcache_size = proc_info->pf.l1dSize;
598 if (proc_info->pf.Available & pfL2) {
599 ml_cpu_info->l2_settings = proc_info->pf.l2cr;
600 ml_cpu_info->l2_cache_size = proc_info->pf.l2Size;
605 if (proc_info->pf.Available & pfL3) {
606 ml_cpu_info->l3_settings = proc_info->pf.l3cr;
607 ml_cpu_info->l3_cache_size = proc_info->pf.l3Size;
625 struct per_proc_info *proc_info;
629 proc_info = PerProcTable[master_cpu].ppe_vaddr;
630 available = proc_info->pf.Available;
633 ccr = proc_info->pf.l2cr;
636 if (enable) ccr = proc_info->pf.l2crOriginal;
638 proc_info->pf.l2cr = ccr;
646 ccr = proc_info->pf.l3cr;
649 if (enable) ccr = proc_info->pf.l3crOriginal;
651 proc_info->pf.l3cr = ccr;
669 struct per_proc_info *proc_info;
675 proc_info = PerProcTable[master_cpu].ppe_vaddr;
677 switch (proc_info->pf.pfPowerModes & pmType) { /* Figure specific type */
784 struct per_proc_info *proc_info;
786 proc_info = PROCESSOR_TO_PER_PROC(processor);
788 if (proc_info != getPerProc()
789 && proc_info->interrupts_enabled == TRUE)
790 cpu_signal(proc_info->cpu_number, SIGPast, (unsigned int)NULL, (unsigned int)NULL);