Lines Matching refs:r20
899 stw r20,tempr0(r11) ; Save some work registers
900 lwz r20,dgFlags(0) ; Get the flags
903 rlwinm r20,r20,MSR_PR_BIT-enaUsrFCallb,MASK(MSR_PR) ; Shift the validity bit over to pr bit spot
905 orc r20,r20,r21 ; Get ~PR | FC
909 andi. r20,r20,MASK(MSR_PR) ; Set cr0_eq is we are in problem state and the validity bit is not set
932 ctgte32: lwarx r20,0,r23 ; Get and reserve the next slot to allocate
933 addi r24,r20,LTR_size ; Point to the next trace entry
947 dcbz 0,r20 ; Clear and allocate first trace line
956 dcbz r24,r20 ; Clean second line
969 sth r24,LTR_cpu(r20) ; Save processor number
971 sth r23,LTR_excpt(r20) ; Set the exception code
972 dcbz r24,r20 ; Clean 3rd line
974 stw r21,LTR_timeHi(r20) ; Save top of time stamp
977 dcbz r24,r20 ; Clean 4th line
978 stw r22,LTR_timeLo(r20) ; Save bottom of time stamp
980 stw r25,LTR_cr(r20) ; Save CR
982 stw r23,LTR_dsisr(r20) ; Save DSISR
983 stw r22,LTR_srr0+4(r20) ; Save SRR0
985 stw r24,LTR_srr1+4(r20) ; Save SRR1
986 stw r23,LTR_dar+4(r20) ; Save DAR
987 stw r21,LTR_lr+4(r20) ; Save LR
989 stw r13,LTR_ctr+4(r20) ; Save CTR
990 stw r0,LTR_r0+4(r20) ; Save register
991 stw r1,LTR_r1+4(r20) ; Save register
992 stw r2,LTR_r2+4(r20) ; Save register
993 stw r3,LTR_r3+4(r20) ; Save register
994 stw r4,LTR_r4+4(r20) ; Save register
995 stw r5,LTR_r5+4(r20) ; Save register
996 stw r6,LTR_r6+4(r20) ; Save register
1000 stw r21,LTR_rsvd0(r20) ; (TEST/DEBUG) Record the owner
1004 addi r21,r20,32 ; Second line
1005 addi r22,r20,64 ; Third line
1006 dcbst 0,r20 ; Force to memory
1015 lwz r20,tempr0(r11) ; Restore work register
1025 lwz r20,tempr0(r11) ; Restore work register
1037 uftct64: std r20,tempr0(r11) ; Save some work registers
1038 lwz r20,dgFlags(0) ; Get the flags
1041 rlwinm r20,r20,MSR_PR_BIT-enaUsrFCallb,MASK(MSR_PR) ; Shift the validity bit over to pr bit spot
1043 orc r20,r20,r21 ; Get ~PR | FC
1047 andi. r20,r20,MASK(MSR_PR) ; Set cr0_eq when we are in problem state and the validity bit is not set
1069 ctgte64: lwarx r20,0,r23 ; Get and reserve the next slot to allocate
1070 addi r24,r20,LTR_size ; Point to the next trace entry
1084 dcbz128 0,r20 ; Zap the trace entry
1098 sth r24,LTR_cpu(r20) ; Save processor number
1099 sth r23,LTR_excpt(r20) ; Set the exception code
1101 std r21,LTR_timeHi(r20) ; Save top of time stamp
1104 stw r25,LTR_cr(r20) ; Save CR
1106 stw r23,LTR_dsisr(r20) ; Save DSISR
1107 std r22,LTR_srr0(r20) ; Save SRR0
1109 std r24,LTR_srr1(r20) ; Save SRR1
1110 std r23,LTR_dar(r20) ; Save DAR
1111 std r21,LTR_lr(r20) ; Save LR
1113 std r13,LTR_ctr(r20) ; Save CTR
1114 std r0,LTR_r0(r20) ; Save register
1115 std r1,LTR_r1(r20) ; Save register
1116 std r2,LTR_r2(r20) ; Save register
1117 std r3,LTR_r3(r20) ; Save register
1118 std r4,LTR_r4(r20) ; Save register
1119 std r5,LTR_r5(r20) ; Save register
1120 std r6,LTR_r6(r20) ; Save register
1124 stw r21,LTR_rsvd0(r20) ; (TEST/DEBUG) Record the owner
1128 dcbf 0,r20 ; Force to memory
1133 ld r20,tempr0(r11) ; Restore work register
1143 ld r20,tempr0(r11) ; Restore work register
1318 dcbz 0,r3 ; allocate 32-byte line with r20-r23
1375 stw r20,saver20+4(r13) ; Save this one
1483 trcsel: lwarx r20,0,r23 ; Get and reserve the next slot to allocate
1485 addi r22,r20,LTR_size ; Point to the next trace entry
1499 dcbz 0,r20 ; Clear and allocate first trace line
1518 dcbz r14,r20 ; Zap the second line
1520 sth r19,LTR_cpu(r20) ; Stash the cpu number
1522 sth r11,LTR_excpt(r20) ; Save the exception type
1526 dcbz r14,r20 ; Zap the third half
1530 stw r16,LTR_timeHi(r20) ; Set the upper part of TB
1531 stw r17,LTR_timeLo(r20) ; Set the lower part of TB
1535 dcbz r14,r20 ; Zap the forth half
1540 stw r8,LTR_cr(r20) ; Save the CR
1543 stw r9,LTR_dsisr(r20) ; Save the DSISR
1544 stw r17,LTR_srr0+4(r20) ; Save the SSR0
1546 stw r18,LTR_srr1+4(r20) ; Save the SRR1
1547 stw r16,LTR_dar+4(r20) ; Save the DAR
1549 stw r13,LTR_save+4(r20) ; Save the savearea
1550 stw r10,LTR_lr+4(r20) ; Save the LR
1552 stw r17,LTR_ctr+4(r20) ; Save off the CTR
1553 stw r0,LTR_r0+4(r20) ; Save off register 0
1554 stw r1,LTR_r1+4(r20) ; Save off register 1
1555 stw r7,LTR_r2+4(r20) ; Save off register 2
1558 stw r3,LTR_r3+4(r20) ; Save off register 3
1559 stw r4,LTR_r4+4(r20) ; Save off register 4
1560 stw r5,LTR_r5+4(r20) ; Save off register 5
1561 stw r6,LTR_r6+4(r20) ; Save off register 6
1564 addi r17,r20,32 ; Second line
1565 addi r16,r20,64 ; Third line
1566 dcbst br0,r20 ; Force to memory
1718 std r20,saver20(r13) ; Save this one
1812 trcselSF: lwarx r20,0,r23 ; Get and reserve the next slot to allocate
1814 addi r22,r20,LTR_size ; Point to the next trace entry
1837 dcbz128 0,r20 ; Zap the trace entry
1843 std r16,LTR_timeHi(r20) ; Set the upper part of TB
1847 std r0,LTR_r0(r20) ; Save off register 0
1850 sth r9,LTR_cpu(r20) ; Stash the cpu number and special flags
1851 std r1,LTR_r1(r20) ; Save off register 1
1853 std r18,LTR_r2(r20) ; Save off register 2
1856 std r3,LTR_r3(r20) ; Save off register 3
1858 std r4,LTR_r4(r20) ; Save off register 4
1860 std r5,LTR_r5(r20) ; Save off register 5
1861 std r6,LTR_r6(r20) ; Save off register 6
1863 stw r16,LTR_cr(r20) ; Save the CR
1864 std r17,LTR_srr0(r20) ; Save the SSR0
1865 std r18,LTR_srr1(r20) ; Save the SRR1
1869 std r17,LTR_dar(r20) ; Save the DAR
1871 std r16,LTR_lr(r20) ; Save the LR
1872 std r17,LTR_ctr(r20) ; Save off the CTR
1874 std r13,LTR_save(r20) ; Save the savearea
1875 stw r17,LTR_dsisr(r20) ; Save the DSISR
1876 sth r11,LTR_excpt(r20) ; Save the exception type
1879 stw r17,LTR_rsvd0(r20) ; (TEST/DEBUG) Record the owner
1883 dcbf 0,r20 ; Force to memory
1958 lwz r20,lo16(xcpTable)(r11) ; Get the interrupt handler (note: xcpTable must be in 1st 32k of physical memory)
1967 mtctr r20 ; Point to the interrupt handler
2045 lwz r20,hwIgnored(r2) ; Grab the ignored interruption count
2046 addi r20,r20,1 ; Count this one
2047 stw r20,hwIgnored(r2) ; Save the ignored count
2058 xcpSyscall: lis r20,hi16(EXT(shandler)) ; Assume this is a normal one, get handler address
2060 ori r20,r20,lo16(EXT(shandler)) ; Assume this is a normal one, get handler address
2421 ld r20,savesrr1(r13) ; Grab the SRR1 so we can decode the thing
2526 rlwinm. r0,r20,0,mckIFUE-32,mckIFUE-32 ; Is this some kind of uncorrectable?
2529 rlwinm. r0,r20,0,mckLDST-32,mckLDST-32 ; Some kind of load/store error?
2532 rldicl. r0,r20,46,62 ; Get the error cause code
2924 PassUpTrap: lis r20,hi16(EXT(thandler)) ; Get thandler address
2925 ori r20,r20,lo16(EXT(thandler)) ; Get thandler address
2928 PassUpRupt: lis r20,hi16(EXT(ihandler)) ; Get ihandler address
2929 ori r20,r20,lo16(EXT(ihandler)) ; Get ihandler address
2934 PassUpFPU: lis r20,hi16(EXT(fpu_switch)) ; Get FPU switcher address
2935 ori r20,r20,lo16(EXT(fpu_switch)) ; Get FPU switcher address
2940 PassUpVMX: lis r20,hi16(EXT(vec_switch)) ; Get VMX switcher address
2941 ori r20,r20,lo16(EXT(vec_switch)) ; Get VMX switcher address
2944 li r20,8 ; Set invalid instruction
2946 sth r20,savesrr1+4(r13) ; Set the invalid instruction SRR code
2953 lis r20,hi16(EXT(chandler)) ; Get choke handler address
2954 ori r20,r20,lo16(EXT(chandler)) ; Get choke handler address
3015 mtsrr0 r20 ; Set up the handler address
3202 dcbt 0,r28 ; touch in r20-r23
3248 lwz r20,saver20+4(r31) ; Restore R20
3492 ld r20,saver20(r31) ; Restore R20