Lines Matching refs:r14
125 mtspr hsprg0,r14 ; Save a register
126 ld r14,UAW(r11) ; Get the User Assist DoubleWord
131 mtsprg 3,r14 ; Set the UAW in sprg3
132 mfspr r14,hsprg0 ; Restore R14
872 uftX64: mtspr hsprg0,r14 ; Save a register in a Hypervisor SPRG
873 ld r14,UAW(r11) ; Get the User Assist DoubleWord
878 mtsprg 3,r14 ; Set the UAW in sprg3
879 mfspr r14,hsprg0 ; Restore R14
1358 stw r14,saver14+4(r13) ; Save this one
1360 la r14,saver24(r13) ; Point to the next block to save into
1366 dcbz 0,r14 ; allocate 32-byte line with r24-r27
1512 li r14,32 ; Offset to second line
1518 dcbz r14,r20 ; Zap the second line
1521 li r14,64 ; Offset to third line
1526 dcbz r14,r20 ; Zap the third half
1529 li r14,96 ; Offset to forth line
1535 dcbz r14,r20 ; Zap the forth half
1574 xcp32xit: mr r14,r11 ; Save the interrupt code across the call
1578 mr r11,r14 ; Get the exception code back
1704 std r14,saver14(r13) ; Save this one
1886 xcp64xit: mr r14,r11 ; Save the interrupt code across the call
1890 mr r11,r14 ; Get the exception code back
1924 addi r14,r10,16 ; Displacement to second vector register
1932 stvxl v1,r14,r2 ; Save a second register
1943 lvxl v1,r14,r2 ; Restore second work register
3152 cmplw cr3,r14,r14 ; Set that we do not need to stop streams
3208 la r14,savectr+4(r31)
3210 dcbt 0,r14 ; touch in CTR, DAR, DSISR, VRSAVE, and Exception code
3215 lwz r14,saver14+4(r31) ; Restore R14
3423 cmplw cr3,r14,r14 ; Set that we do not need to stop streams
3467 ld r14,saver14(r31) ; Restore R14