Lines Matching refs:mtspr
125 mtspr hsprg0,r14 ; Save a register
164 mtspr hid4,r11 ; ?
171 mtspr hid4,r13 ; ?
199 mtspr msscr0,r11 ; ?
872 uftX64: mtspr hsprg0,r14 ; Save a register in a Hypervisor SPRG
1245 mtspr hid0,r2 ; Clear the nap/doze bits
1345 mtspr hid1,r3 ; Restore HID1
1352 mtspr msscr0,r3 ; Restore MSSCR0
1415 mtspr pmc5,r22 ; Leave PMC5 clear
1416 mtspr pmc6,r22 ; Leave PMC6 clear
1421 mtspr mmcr2,r22 ; Leave MMCR2 clear
1428 mtspr mmcr0,r22 ; Leave MMCR0 clear
1429 mtspr mmcr1,r22 ; Leave MMCR1 clear
1438 mtspr pmc1,r22 ; Leave PMC1 clear
1439 mtspr pmc2,r22 ; Leave PMC2 clear
1440 mtspr pmc3,r22 ; Leave PMC3 clear
1441 mtspr pmc4,r22 ; Leave PMC4 clear
1632 mtspr hid0,r3 ; Set the updated hid0
1752 mtspr mmcr0_gp,r22 ; Leave MMCR0 clear
1753 mtspr mmcr1_gp,r22 ; Leave MMCR1 clear
1754 mtspr mmcra_gp,r22 ; Leave MMCRA clear
1771 mtspr pmc1_gp,r22 ; Leave PMC1 clear
1772 mtspr pmc2_gp,r22 ; Leave PMC2 clear
1773 mtspr pmc3_gp,r22 ; Leave PMC3 clear
1774 mtspr pmc4_gp,r22 ; Leave PMC4 clear
1775 mtspr pmc5_gp,r22 ; Leave PMC5 clear
1776 mtspr pmc6_gp,r22 ; Leave PMC6 clear
1777 mtspr pmc7_gp,r22 ; Leave PMC7 clear
1778 mtspr pmc8_gp,r22 ; Leave PMC8 clear
1940 mtspr vrsave,r9 ; Clear VRSAVE for each interrupt level
2156 mtspr dabr,r0 ; (BRINGUP)
2214 mtspr dabr,r10 ; (BRINGUP)
2432 mtspr scomc,r8 ; Request the MCK source
2443 mtspr scomd,r9 ; Set the AND mask to 0
2444 mtspr scomc,r8 ; Write the AND mask and clear conditions
2454 mtspr scomc,r8 ; Request the Core FIR
2464 mtspr scomd,r9 ; Set the AND mask to 0
2465 mtspr scomc,r8 ; Write the AND mask and clear conditions
2475 mtspr scomc,r8 ; Request the L2 FIR
2485 mtspr scomd,r9 ; Set the AND mask to 0
2486 mtspr scomc,r8 ; Write the AND mask and clear conditions
2496 mtspr scomc,r8 ; Request the Bus FIR
2506 mtspr scomd,r9 ; Set the AND mask to 0
2507 mtspr scomc,r8 ; Write the AND mask and clear conditions
2736 mtspr hid1,r0 ; Stick it
2737 mtspr hid1,r0 ; Stick it again
2748 mtspr hid1,r21 ; Restore original HID1
2749 mtspr hid1,r21 ; Stick it again
3232 mtspr vrsave,r27 ; Set the vrsave
3271 mtspr pmc5,r28 ; Restore PMC5
3272 mtspr pmc6,r29 ; Restore PMC6
3276 mtspr mmcr2,r28 ; Restore MMCR2
3281 mtspr pmc1,r28 ; Restore PMC1
3282 mtspr pmc2,r29 ; Restore PMC2
3285 mtspr pmc3,r28 ; Restore PMC3
3286 mtspr pmc4,r29 ; Restore PMC4
3289 mtspr mmcr1,r28 ; Restore MMCR1
3290 mtspr mmcr0,r29 ; Restore MMCR0
3479 noavec2s: mtspr vrsave,r27 ; Set the vrsave
3514 mtspr pmc1_gp,r28 ; Restore PMC1
3515 mtspr pmc2_gp,r29 ; Restore PMC2
3518 mtspr pmc3_gp,r28 ; Restore PMC3
3519 mtspr pmc4_gp,r29 ; Restore PMC4
3522 mtspr pmc5_gp,r28 ; Restore PMC5
3523 mtspr pmc6_gp,r29 ; Restore PMC6
3526 mtspr pmc7_gp,r28 ; Restore PMC7
3527 mtspr pmc8_gp,r29 ; Restore PMC8
3530 mtspr mmcr1_gp,r28 ; Restore MMCR1
3531 mtspr mmcra_gp,r29 ; Restore MMCRA
3534 mtspr mmcr0_gp,r28 ; Restore MMCR0
3548 mtspr hsprg0,r28 ; Save R30 for later