Lines Matching refs:is
66 ; waking up from sleep), a RESET_HANDLER_BUPOR (which is using for bring up
71 ; The ones who do take it, check if the interrupt is too be ignored. This is
72 ; always the case until the previous reset is handled (i.e., we have exited
152 LEXT(extPatchMCK) ; This is patched to a nop for 64-bit
350 ; The syscall number is in r0. All we do here is munge the number into an
352 ; Fast Traps (UFTs.) The index is:
354 ; 0x80 - set if syscall number is 0x80000000 (CutTrace)
355 ; 0x40 - set if syscall number is 0x00006004
359 ; 0x01 - zero, as scTable is an array of shorts
367 addi r11,r11,8 ; make a 0 iff this is a 0xFFFFFFF8 trap
389 * is also done here now. while this is permanently in the
390 * system the impact is completely unnoticable as this code is
391 * only executed when (a) a single step or branch exception is
392 * hit, (b) in the single step debugger case there is so much
396 * Note that this trace is available only to user state so we do not
552 * There is now a large gap of reserved traps
582 * 1. If (syscall & 0xFFFFF000) == 0x00007000, then it is a PPC Fast Trap or UFT.
585 * 2. If (syscall & 0xFFFFF000) == 0x00006000, then it is a PPC-only trap.
586 * One of these (0x6004) is a UFT, but most are dispatched in hw_exceptions.s. These
589 * 3. If (syscall & 0xFFFFFFF0) == 0xFFFFFFF0, then it is also a UFT and is dispatched here.
591 * 4. If (syscall & 0xFFFFF000) == 0x80000000, then it is a "firmware" call and is dispatched in
592 * Firmware.s, though the special "Cut Trace" trap (0x80000000) is handled here as an ultra
595 * 5. If (syscall & 0xFFFFF000) == 0xFFFFF000, and it is not one of the above, then it is a Mach
598 * 6. If (syscall & 0xFFFFF000) == 0x00000000, then it is a BSD syscall, which are dispatched
601 * What distinguishes the UFTs, aside from being ultra fast, is that they cannot rely on translation
612 * "scTable" is an array of 2-byte addresses, accessed using a 7-bit index derived from the syscall
615 * 0x80 (A) - set if syscall number is 0x80000000
616 * 0x40 (B) - set if syscall number is 0x00006004
637 .short uftNormalSyscall-baseR ; 0001 0 0x7FF0 is unassigned
638 .short uftNormalSyscall-baseR ; 0001 1 0x7FF1 is Set Thread Info Fast Trap (pass up)
639 .short uftThreadInfo-baseR ; 0001 2 0x7FF2 is Thread Info
640 .short uftFacilityStatus-baseR ; 0001 3 0x7FF3 is Facility Status
641 .short uftLoadMSR-baseR ; 0001 4 0x7FF4 is Load MSR
642 .short uftNormalSyscall-baseR ; 0001 5 0x7FF5 is the Null FastPath Trap (pass up)
643 .short uftNormalSyscall-baseR ; 0001 6 0x7FF6 is unassigned
644 .short uftNormalSyscall-baseR ; 0001 7 0x7FF7 is unassigned
646 .short uftNormalSyscall-baseR ; 0010 0 0xFFFFFFF0 is unassigned
647 .short uftNormalSyscall-baseR ; 0010 1 0xFFFFFFF1 is unassigned
648 .short uftNormalSyscall-baseR ; 0010 2 0xFFFFFFF2 is unassigned
649 .short uftNormalSyscall-baseR ; 0010 3 0xFFFFFFF3 is unassigned
650 .short uftNormalSyscall-baseR ; 0010 4 0xFFFFFFF4 is unassigned
651 .short uftNormalSyscall-baseR ; 0010 5 0xFFFFFFF5 is unassigned
652 .short uftIsPreemptiveTaskEnv-baseR ; 0010 6 0xFFFFFFFE is Blue Box uftIsPreemptiveTaskEnv
653 .short uftIsPreemptiveTask-baseR ; 0010 7 0xFFFFFFFF is Blue Box IsPreemptiveTask
664 .short WhoaBaby-baseR ; 0100 0 0x6000 is an impossible index (diagCall)
665 .short WhoaBaby-baseR ; 0100 1 0x6001 is an impossible index (vmm_get_version)
666 .short WhoaBaby-baseR ; 0100 2 0x6002 is an impossible index (vmm_get_features)
667 .short WhoaBaby-baseR ; 0100 3 0x6003 is an impossible index (vmm_init_context)
668 .short uftVMM-baseR ; 0100 4 0x6004 is vmm_dispatch (only some of which are UFTs)
669 .short WhoaBaby-baseR ; 0100 5 0x6005 is an impossible index (bb_enable_bluebox)
670 .short WhoaBaby-baseR ; 0100 6 0x6006 is an impossible index (bb_disable_bluebox)
671 .short WhoaBaby-baseR ; 0100 7 0x6007 is an impossible index (bb_settaskenv)
814 cmpwi r0,-2 ; is this call IsPreemptiveTaskEnv?
841 ; Handle "Load MSR" UFT (0x7FF4). This is not used on 64-bit processors, though it would work.
888 ; An identical entry is made during normal interrupt processing. Any entry
909 andi. r20,r20,MASK(MSR_PR) ; Set cr0_eq is we are in problem state and the validity bit is not set
922 ; Since we do not lock the actual trace buffer, there is a potential that
930 beq-- ctdisa32 ; Leave because tracing is disabled...
962 ; An identical entry is made during normal interrupt processing. Any entry
1034 ; This is the 64-bit version.
1047 andi. r20,r20,MASK(MSR_PR) ; Set cr0_eq when we are in problem state and the validity bit is not set
1059 ; Since we do not lock the actual trace buffer, there is a potential that
1067 beq-- ctdisa64 ; Leave because tracing is disabled...
1092 ; An identical entry is made during normal interrupt processing. Any entry
1154 ; Handle a system call that is not a UFT and which thus goes upstairs.
1167 li r11,T_SYSTEM_CALL|T_FAM ; this is a system call (and fall through)
1191 * misses, so these stores won't take all that long. Except the first line that is because
1192 * we can't do a DCBZ if the L1 D-cache is off. The rest we will skip if they are
1237 ; This is the 32-bit context saving stuff
1407 beq cr1,perfMonSave32_750 ; This is a G3...
1451 ; Everything is saved at this point, except for FPRs, and VMX registers.
1452 ; Time for us to get a new savearea and then trace interrupt if it is enabled.
1467 crandc cr5_eq,cr5_eq,cr0_eq ; Turn off tracing if cpu is disabled
1476 ; Since we do not lock the actual trace buffer, there is a potential that
1505 ; An identical entry is made during normal CutTrace processing. Any entry
1533 mfsrr0 r17 ; Get SRR0 back, it is still good
1538 mfsrr1 r18 ; SRR1 is still good in here
1586 ; This is the 64-bit context saving stuff
1633 mfspr r1,hid0 ; Yes, this is silly, keep it here
1634 mfspr r1,hid0 ; Yes, this is a duplicate, keep it here
1635 mfspr r1,hid0 ; Yes, this is a duplicate, keep it here
1636 mfspr r1,hid0 ; Yes, this is a duplicate, keep it here
1637 mfspr r1,hid0 ; Yes, this is a duplicate, keep it here
1638 mfspr r1,hid0 ; Yes, this is a duplicate, keep it here
1783 ; Everything is saved at this point, except for FPRs, and VMX registers.
1784 ; Time for us to get a new savearea and then trace interrupt if it is enabled.
1799 crandc cr5_eq,cr5_eq,cr0_eq ; Turn off tracing if cpu is disabled
1805 ; Since we do not lock the actual trace buffer, there is a potential that
1833 ; An identical entry is made during normal CutTrace processing. Any entry
1859 mfsrr0 r17 ; Get SRR0 back, it is still good
1862 mfsrr1 r18 ; SRR1 is still good in here
1896 ; All of the context is saved. Now we will get a
1907 ; Note that we assume that emfp0 is on an altivec boundary
1910 ; We need to save the FPSCR as if it is normal context.
1911 ; This is because pending exceptions will cause an exception even if
1912 ; FP is disabled. We need to clear the FPSCR when we first start running in the
1970 add r23,r23,r22 ; Count this one if if is a redrive
1974 bne-- cr3,IgnoreRupt ; Interruption is being ignored...
2058 xcpSyscall: lis r20,hi16(EXT(shandler)) ; Assume this is a normal one, get handler address
2060 ori r20,r20,lo16(EXT(shandler)) ; Assume this is a normal one, get handler address
2072 FCisok: beq++ cr2,EatRupt ; This is a CutTrace system call, we are done with it...
2075 ; Here is where we call the firmware. If it returns T_IN_VAIN, that means
2077 ; while you are away. Anything else is ok.
2084 ; Here is where we return from the firmware call
2098 ; Here is where we return from the PTE miss and segment exception handler
2294 NoFamPf: andi. r4,r0,lo16(MASK(MSR_RI)) ; See if the recover bit is on
2299 ; Here is where we handle the "recovery mode" stuff.
2300 ; This is set by an emulation routine to trap any faults when it is fetching data or
2325 ; Here is where we handle the context switch firmware call. The old
2326 ; context has been saved. The new savearea is in kind of hokey, the high order
2327 ; half is stored in saver7 and the low half is in saver3. We will just
2367 ; ml_probe_read. If so, this is expected, so modify the PC to
2515 beq++ mckNoFix ; No fix up is needed
2536 blt mckSLBparity ; This is an SLB parity error...
2537 bgt mckhIFUE ; This is an IFetch tablewalk reload UE...
2546 ; SLB parity error. This could be software caused. We get one if there is
2558 andis. r0,r6,0x0800 ; See if valid bit is on
2581 slbia ; Trash all SLB entries (except for entry 0 that is)
2582 slbmfee r7,r0 ; Get the entry that is in SLB index 0
2617 ; This is a recoverable D-ERAT or TLB error
2632 ; When we come here, we are not quite sure what the error is. We need to
2635 ; R24 is interrupt source
2636 ; R25 is Core FIR
2652 ; We really do not know what this one is or what to do with it...
2661 ; Hang recovery. This is just a notification so we only count.
2681 ; Machine check cause is in a FIR. Suss it out here.
2682 ; Core FIR is in R25 and has been cleared in HW.
2765 ; General hang recovery - this is a notification only, just count.
2793 ; Right here is where we end up after a failure on a ml_probe_read_64.
2794 ; We will check if that is the case, and if so, fix everything up and
2808 blt-- ueMck ; This is a normal machine check, just pass up...
2843 ; When the program check is a trap instruction and it happens when
2844 ; we are executing injected code, we need to check if it is an exit trap.
2845 ; If it is, we need to populate the current savearea with some of the context from
2846 ; the saved pre-inject savearea. This is needed because the current savearea will be
2860 rlwimi. r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits and see if ijsave is 0
2864 bne++ cr0,mustem ; This is not an injection exit...
2891 * T_IN_VAIN, the emulation is done and we should just reload state and directly
2917 ; We assume kernel data is mapped contiguously in physical
2943 li r11,T_PROGRAM ; Say that it is a program exception
2966 rlwimi. r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits and see if ijsave is 0
3025 * This routine is the main place where we return from an interruption.
3027 * This is also where we release the quickfret list. These are saveareas
3031 * is in flux and should not be looked at here. This comes into play only
3033 * Quite rare but could happen. If the flag is set, this code does not
3036 * All we need to remember here is that R13 must point to the savearea
3042 * is any tomfoolery with savearea stacks, it must be taken care of
3071 stw r30,quickfret+4(r29) ; Dequeue previous guy (really, it is ok to wait until after the release)
3084 ; Important!!!! The savearea is released before we are done with it. When the
3093 ; we will continue to use it. The code stream to inject is in it and we
3095 ; post-inject context. The field ijsave in the per-proc is used to point to the savearea.
3104 ; SAVinject is set. That means that if will not run if we are returning from an alignment
3254 dcbz 0,r26 ; Clear and allocate next savearea we use in the off chance it is still in when we next interrupt
3266 beq- cr1,perfMonRestore32_750 ; This is a G3...
3314 rfi ; Click heels three times and think very hard that there is no place like home...
3344 std r30,quickfret(r29) ; Dequeue previous guy (really, it is ok to wait until after the release)
3356 ; Important!!!! The savearea is released before we are done with it. When the
3365 ; we will continue to use it. The code stream to inject is in it and we
3367 ; post-inject context. The field ijsave in the per-proc is used to point to the savearea.
3376 ; SAVinject is set. That means that if will not run if we are returning from an alignment
3504 dcbz128 0,r26 ; Clear and allocate next savearea we use in the off chance it is still in when we next interrupt
3560 rfid ; Click heels three times and think very hard that there is no place like home...
3645 ; Here is where we keep the low memory globals
3974 ; The "shared page" is used for low-level debugging and is actually 1/2 page long
3980 EXT(sharedPage): ; This is a debugging page shared by all processors
3993 ; The ijcode area is used for code injection. It is 1/2 page long and will allow 32 processors to inject