Lines Matching refs:r19
144 stw r19,FM_ARG0+0x08(r1) ; Save a register
145 mfsprg r19,2 ; Get feature flags
148 mtcrf 0x02,r19 ; move pf64Bit cr6
353 lwz r19,FM_ARG0+0x08(r1) ; Save a register
531 stw r19,FM_ARG0+0x10(r1) ; Save a register
532 mfsprg r19,2 ; Get feature flags
535 mtcrf 0x02,r19 ; move pf64Bit cr6
571 mfsprg r19,2 ; Get feature flags again (for alternate entries)
710 rlwinm. r0,r19,0,pfSMPcapb,pfSMPcapb ; Can this processor do SMP?
849 lwz r19,FM_ARG0+0x10(r1) ; Restore a register
1027 rlwinm. r0,r19,0,pfSMPcapb,pfSMPcapb ; Can this processor do SMP?
1461 ; r19: sprg2 (feature flags)
1751 stw r19,FM_ARG0+0x10(r1) ; Save a register
1862 stw r19,FM_ARG0+0x10(r1) ; Save a register
1863 mfsprg r19,2 ; Get feature flags
1866 mtcrf 0x02,r19 ; move pf64Bit cr6
1982 stw r19,FM_ARG0+0x10(r1) ; Save a register
2130 stw r19,FM_ARG0+0x10(r1) ; Save a register
3772 mr r19,r2 ; Remember the per_proc
3776 la r8,ppUserPmap(r19) ; Point to the current user pmap
3956 la r31,ppUMWmp(r19) ; Just point to the mapping
4116 lwz r4,ppMapFlags(r19) ; Get the protection key modifier
4123 lwz r16,validSegs(r19) ; Get the valid SR flags
4135 stw r16,validSegs(r19) ; Set the valid SR flags
4149 ld r16,validSegs(r19) ; Get the valid SLB entry flags
4168 lwz r4,ppSegSteal(r19) ; Get the next slot to steal
4179 stw r4,ppSegSteal(r19) ; Set the next slot to steal
4197 std r16,validSegs(r19) ; Mark as valid
4274 xor r19,r15,r0 ; Calculate hash << 12
4283 rlwinm r19,r19,26,6,25 ; Shift hash over to make offset into hash table
4287 and r19,r19,r16 ; Wrap hash table offset into the hash table
4289 rlwinm r20,r19,28,10,29 ; Shift hash over to make offset into PCA
4290 add r19,r19,r27 ; Point to the PTEG
4335 rlwimi r19,r4,3,26,28 ; Insert PTE index into PTEG address yielding PTE address
4339 lwz r6,0(r19) ; Get the old PTE
4340 lwz r7,4(r19) ; Get the real part of the stealee
4350 hpfNipBM: stw r6,0(r19) ; Set the invalid PTE
4364 srwi r0,r19,6 ; Align PTEG offset for back hash
4395 lwz r4,4(r19) ; Get the RC of the just invalidated PTE
4421 hpfFPnch2: sub r0,r19,r27 ; Get offset to the PTEG
4427 stw r24,4(r19) ; Stuff in the real part of the PTE
4430 stw r18,0(r19) ; Stuff the virtual part of the PTE and make it valid
4467 xor r19,r0,r15 ; Calculate hash
4470 srdi r19,r19,5 ; Convert page offset to hash table offset
4475 and r19,r19,r16 ; Wrap into hash table
4477 srdi r20,r19,5 ; Convert PTEG offset to PCA offset
4482 add r19,r19,r27 ; Point to the PTEG
4525 insrdi r19,r4,3,57 ; Insert slot index into PTEG address bits 57:59, forming the PTE address
4529 ld r6,0(r19) ; Get the old PTE
4530 ld r7,8(r19) ; Get the real part of the stealee
4540 hpfNipBMx: std r6,0(r19) ; Set the invalid PTE
4545 xor r11,r11,r19 ; Hash backwards to get low bits of VPN
4584 ld r12,8(r19) ; Get the RC of the just invalidated PTE
4623 hpfFPnch2x: sub r0,r19,r27 ; Get offset to PTEG
4628 hpfInser64: std r24,8(r19) ; Stuff in the real part of the PTE
4630 std r15,0(r19) ; Stuff the virtual part of the PTE and make it valid
4645 hpfFinish: sub r4,r19,r27 ; Get offset of PTE
5498 la r19,ppUserPmap(r29) ; Point to the current user pmap
5504 and r19,r19,r3 ; Zero user pmap ptr if kernel, untouched otherwise
5506 or r8,r8,r19 ; Get the pointer to the pmap we are using