Lines Matching refs:bit
72 ; +--------+--------+--------+ for 65 bit VPN
170 bt++ pf64Bitb,hamSF1 ; skip if 64-bit (only they take the hint)
179 hamSF1x: bl EXT(mapSetUp) ; Turn off interrupts, translation, and possibly enter 64-bit
216 add r0,r0,r0 ; Get 0xFFFFFFFF00000000 for 64-bit or 0 for 32-bit
219 or r0,r30,r0 ; Fill high word of 64-bit with 1s so we will properly carry
288 rlwimi r10,r29,18,0,13 ; Shift EA[18:31] down to VSID (31-bit math works because of max hash table size)
299 bt++ pf64Bitb,ham64 ; This is 64-bit...
438 * a 64-bit quantity, it is a long long so it is in R4 and R5.
443 * Note that this is designed to be called from 32-bit mode with a stack.
555 bt++ pf64Bitb,hrmSF1 ; skip if 64-bit (only they take the hint)
562 bl EXT(mapSetUp) ; Turn off interrupts, translation, and possibly enter 64-bit
656 ; Here is also where we need to split 32- and 64-bit processing
660 rlwinm r23,r29,0,1,0 ; Copy high order vaddr to high if 64-bit machine
668 ori r2,r2,0xFFFF ; Get mask to clean out hash table base (works for both 32- and 64-bit)
670 rlwinm r21,r21,0,~mpHValid ; Clear out valid bit
678 bt++ pf64Bitb,hrmSplit64 ; Go do 64-bit version...
692 rlwinm r21,r21,0,~mpHValid ; Clear out valid bit
693 rlwinm r5,r5,0,1,31 ; Turn off valid bit in PTE
723 lis r0,0x8000 ; Get bit for slot 0
724 eieio ; Make sure those RC bit have been stashed in PTE
809 hrmErRtn: bt++ pf64Bitb,hrmSF1z ; skip if 64-bit (only they take the hint)
862 rlwinm r3,r3,0,0,31 ; Clear top of register if 64-bit
891 ; PTEG up to the point where we have cleared it all (64 for 32-bit architecture)
922 stb r0,mpFlags+3(r31) ; Save the flags with the mpRIP bit on
1095 ; Here we handle the 64-bit version of hw_rem_map
1112 rlwinm r21,r21,0,~mpHValid ; Clear out valid bit
1114 // **** Need to adjust above shift based on the page size - large pages need to shift a bit more
1115 rldicr r5,r5,0,62 ; Clear the valid bit
1256 stb r0,mpFlags+3(r31) ; Save the flags with the mpRIP bit on
1288 rlwinm r3,r23,27,5,29 ; Change to PCA offset (table is always 2GB or less so 32-bit instructions work here)
1476 rlwinm r30,r30,0,0xFFFFF000 ; Clean up low-order bits of 32-bit guest vaddr
1477 bt++ pf64Bitb,hrmG64 ; Test for 64-bit machine
1484 rldimi r30,r29,32,0 ; Insert high-order 32 bits of 64-bit guest vaddr
1500 bt++ pf64Bitb,hrmG64Search ; Separate handling for 64-bit search
1592 bt++ pf64Bitb,hrmGDscon64 ; Handle 64-bit disconnect separately
1601 b hrmGFreePTE ; Join 64-bit path to release the PTE
1608 lis r0,0x8000 ; Prepare free bit for this slot
1609 srw r0,r0,r2 ; Position free bit
1624 bt++ pf64Bitb,hrmGRemove64 ; Use 64-bit version on 64-bit machine
1627 rlwinm. r9,r9,0,~ppFlags ; Remove flags, yielding 32-bit physical chain pointer
1654 andc. r9,r9,r7 ; Remove flags, yielding 64-bit physical chain pointer
1692 bt++ pf64Bitb,hrmGRtn64 ; Handle 64-bit separately
1696 hrmGRtn64: mtmsrd r17 ; Restore 'rupts, translation, 32-bit mode
1722 * Note that this is designed to be called from 32-bit mode with a stack.
1768 bl EXT(mapSetUp) ; Turn off interrupts, translation, and possibly enter 64-bit
1772 bt++ pf64Bitb,hppSF ; skip if 64-bit (only they take the hint)
1799 bt++ pf64Bitb,hppSF2 ; skip if 64-bit (only they take the hint)
1811 bt++ pf64Bitb,hppSF3 ; skip if 64-bit (only they take the hint)...
1835 * a 64-bit quantity, it is a long long so it is in R4 and R5.
1840 * Note that this is designed to be called from 32-bit mode with a stack.
1886 bt++ pf64Bitb,hpmSF1 ; skip if 64-bit (only they take the hint)
1893 bl EXT(mapSetUp) ; Turn off interrupts, translation, and possibly enter 64-bit
1952 * Note that this is designed to be called from 32-bit mode with a stack.
2006 bt++ pf64Bitb,hpsSF1 ; skip if 64-bit (only they take the hint)
2014 hpsSF1x: bl EXT(mapSetUp) ; Turn off interrupts, translation, and possibly enter 64-bit
2022 bt++ pf64Bitb,hpsSF ; skip if 64-bit (only they take the hint)
2067 bt++ pf64Bitb,hpsSF3 ; skip if 64-bit (only they take the hint)...
2104 * r3 : physent, 32-bit kernel virtual address
2105 * r4 : host pmap, 32-bit kernel virtual address
2150 bt++ pf64Bitb,hsg64Salt ; Test for 64-bit machine
2152 lwz r9,pmapvr+4(r4) ; Get 32-bit virt<->real conversion salt
2156 ld r9,pmapvr+4(r4) ; Get 64-bit virt<->real conversion salt
2158 hsgStart: bl EXT(mapSetUp) ; Disable 'rupts, translation, enter 64-bit mode
2162 bt++ pf64Bitb,hsg64Scan ; Test for 64-bit machine
2242 * Note that this is designed to be called from 32-bit mode with a stack.
2259 bl EXT(mapSetUp) ; Turn off interrupts, translation, and possibly enter 64-bit
2263 bt++ pf64Bitb,hfsSF ; skip if 64-bit (only they take the hint)
2314 hfsRet: bt++ pf64Bitb,hfsSF3 ; skip if 64-bit (only they take the hint)...
2381 bl EXT(mapSetUp) ; Turn off interrupts, translation, and possibly enter 64-bit
2386 xor r28,r3,r7 ; Change the common 32- and 64-bit half
2388 bf-- pf64Bitb,hfmSF1 ; skip if 32-bit...
2406 rlwinm r0,r7,0,mpRIPb,mpRIPb ; Find remove in progress bit
2421 ; Note: we can treat 32- and 64-bit the same here. Because we are going from
2422 ; physical to virtual and we only do 32-bit virtual, we only need the low order
2432 rlwinm r3,r31,0,0,31 ; Move mapping to return register and clear top of register if 64-bit
2484 bl EXT(mapSetUp) ; Turn off interrupts, translation, and possibly enter 64-bit
2502 bt++ pf64Bitb,hcmNextPhys64 ; 64-bit version
2514 rlwinm r0,r0,0,~mpHValid ; Clear out valid bit
2536 rlwinm r0,r0,0,~mpHValid ; Clear out valid bit
2552 bt++ pf64Bitb,hcmDone64 ; 64-bit version
2581 * Note that this is designed to be called from 32-bit mode with a stack.
2615 bl EXT(mapSetUp) ; Turn off interrupts, translation, and possibly enter 64-bit
2642 bt++ pf64Bitb,hwp64 ; skip if 64-bit (only they take the hint)
2925 ; Copy in the cache inhibited bit
2929 ; Copy in the guarded bit
2969 hwpCRefMap: li r0,lo16(mpR) ; Get reference bit
2996 hwpCCngMap: li r0,lo16(mpC) ; Get change bit
3036 ori r4,r4,lo16(ppC) ; Set the change bit
3057 rlwinm. r0,r0,0,ppRb-32,ppRb-32 ; Isolate reference bit and see if 0
3065 hwpTRefMap: rlwinm. r0,r5,0,mpRb-32,mpRb-32 ; Isolate reference bit and see if 0
3074 rlwinm. r0,r0,0,ppCb-32,ppCb-32 ; Isolate change bit and see if 0
3082 hwpTCngMap: rlwinm. r0,r5,0,mpCb-32,mpCb-32 ; Isolate change bit and see if 0
3176 bl EXT(mapSetUp) ; Turn off interrupts, translation, and possibly enter 64-bit
3181 xor r28,r3,r7 ; Change the common 32- and 64-bit half
3183 bf-- pf64Bitb,hpSF1 ; skip if 32-bit...
3213 bt++ pf64Bitb,hpDo64 ; Split for 64 bit
3217 rlwimi r5,r24,0,mpPPb-32,mpPPe-32 ; Stick in the new pp (note that we ignore no-execute for 32-bit)
3354 bl EXT(mapSetUp) ; Turn off interrupts, translation, and possibly enter 64-bit
3359 xor r28,r3,r7 ; Change the common 32- and 64-bit half
3361 bf-- pf64Bitb,htrSF1 ; skip if 32-bit...
3389 bt++ pf64Bitb,htrDo64 ; Split for 64 bit
3564 oris r0,r2,0x8000 ; Set the lock bit
3580 rlwinm r0,r0,0,1,31 ; Clear the lock bit
3695 ; that the hash bit is not set. This forces the fault code
3732 * bit must be set in the DSISR (or SRR1 for IFETCH). That must occur
3780 bt-- pf64Bitb,hpf64a ; If 64-bit, skip the next bit...
3783 ; On 32-bit machines we emulate a segment exception by loading unused SRs with a
3785 ; we turn off the PTE miss bit in the DSISR to drive the code later on that will
3798 rlwinm r27,r27,0,dsiMissb+1,dsiMissb-1 ; Clear the PTE miss bit in DSISR
3807 hpf64a: ld r28,0(r8) ; Get the pmap pointer (64-bit)
3860 add r0,r0,r0 ; Get 0xFFFFFFFF00000000 for 64-bit or 0 for 32-bit
3862 or r23,r23,r0 ; Make sure a carry will propagate all the way in 64-bit
3869 rlwinm r23,r23,0,0,31 ; Clean up the relocated address (does nothing in 32-bit)
3874 bt++ pf64Bitb,hpfGetPmap64 ; Separate handling for 64-bit machines
4007 rlwinm r14,r14,12,15,19 ; Slide the top of the VSID over to correct position (trim for 65 bit addressing)
4033 ; also update the pmap sub-tag as well. The sub-tag is a table of 4 bit
4034 ; entries that correspond to the last 4 bits (32:35 for 64-bit and
4035 ; 0:3 for 32-bit) of the ESID.
4043 ; 64-bit architecture. For 32-bit, it is a simple transform to an SR image.
4048 ; Also remember that we do not store the valid bit in the ESID. If we
4073 and r7,r7,r6 ; Clear bit number if none empty
4079 oris r8,r8,0x8000 ; Get the high bit on
4099 andc r4,r4,r8 ; Clear the invalid bit for the slot we just allocated
4117 bt++ pf64Bitb,hpfLoadSeg64 ; If 64-bit, go load the segment...
4120 ; Make and enter 32-bit segment register
4126 rlwinm r6,r12,19,1,3 ; Insert the keys and N bit
4127 lis r0,0x8000 ; Set bit 0
4129 srw r0,r0,r2 ; Get bit corresponding to SR
4140 ; Make and enter 64-bit segment look-aside buffer entry.
4141 ; Note that the cache entry is the right format except for valid bit.
4142 ; We also need to convert from long long to 64-bit register values.
4154 li r0,1 ; Prepare to set bit 0
4158 or r9,r8,r30 ; Form full 64-bit address
4160 sldi r0,r0,63 ; Get bit 0 set
4173 rldicr r7,r7,0,35 ; Clear the valid bit and the rest
4187 srd r0,r0,r4 ; Set bit mask for allocation
4188 oris r9,r9,0x0800 ; Turn on the valid bit
4230 li r3,mpHValid ; Get the PTE valid bit
4234 and. r12,r12,r3 ; Isolate the valid bit
4243 bt++ pf64Bitb,hpfBldPTE64 ; Skip down to the 64 bit stuff...
4246 ; At this point we are about to do the 32-bit PTE generation.
4256 ; The 24 bits of the 32-bit architecture VSID is in the following:
4267 lwz r25,mpVAddr+4(r31) ; Grab the base virtual address for the mapping (32-bit portion)
4279 slwi r24,r24,12 ; Change ppnum to physical address (note: 36-bit addressing no supported)
4288 ori r24,r24,lo16(mpR) ; Turn on the reference bit right now
4292 oris r18,r18,lo16(0x8000) ; Make sure the valid bit is on
4341 rlwinm r6,r6,0,1,31 ; Clear the valid bit
4425 hpfInser32: oris r18,r18,lo16(0x8000) ; Make sure the valid bit is on
4436 ; At this point we are about to do the 64-bit PTE generation.
4462 or r11,r11,r23 ; Stick in bottom of adjusted EA for full 64-bit value
4464 or r15,r15,r14 ; Stick in bottom of AVPN for full 64-bit value
4468 ori r15,r15,1 ; Turn on valid bit in AVPN to make top of PTE
4480 ori r24,r24,lo16(mpR) ; Force on the reference bit
4531 rldicr r6,r6,0,62 ; Clear the valid bit
4646 ori r4,r4,lo16(mpHValid) ; Add valid bit to PTE offset
4699 ; linear list of 64-bit physical addresses of the pages that comprise
4712 bt pf64Bitb,hpfGV64 ; Take 64-bit path for 64-bit machine
4780 rlwinm r10,r30,0,0xFFFFF000 ; Form 64-bit guest vaddr
4910 /* int mapalc1(struct mappingblok *mb) - Finds, allocates, and zeros a free 1-bit mapping entry
4916 * when n and -n are returned, the corresponding bit is cleared
4926 lis r0,0x8000 ; Get the mask to clear the first free bit
4929 cntlzw r3,r4 ; Get first 1-bit in 1st word
4930 srw. r9,r0,r3 ; Get bit corresponding to first free one
4932 andc r4,r4,r9 ; Turn 1-bit off in 1st word
4935 srw. r9,r0,r10 ; Get bit corresponding to first free one in 2nd word
4951 bnelr++ ; return if another bit remains set
4953 neg r3,r3 ; indicate we just returned the last bit
4957 /* int mapalc2(struct mappingblok *mb) - Finds, allocates, and zero's a free 2-bit mapping entry
4972 lis r0,0x8000 ; Get the mask to clear the first free bit
4976 and r6,r4,r6 ; lite start of double bit runs in 1st word
4978 cntlzw r3,r6 ; Get first free 2-bit run in 1st word
4979 and r7,r5,r7 ; lite start of double bit runs in 2nd word
4980 srw. r9,r0,r3 ; Get bit corresponding to first run in 1st word
4982 srwi r11,r9,1 ; shift over for 2nd bit in 1st word
4983 andc r4,r4,r9 ; Turn off 1st bit in 1st word
4984 andc r4,r4,r11 ; turn off 2nd bit in 1st word
4987 srw. r9,r0,r10 ; Get bit corresponding to first free one in second word
4989 srwi r11,r9,1 ; get mask for 2nd bit
4990 andc r5,r5,r9 ; Turn off 1st bit in 2nd word
4991 andc r5,r5,r11 ; turn off 2nd bit in 2nd word
5004 dcbz r7,r12 ; we use the slow 32-byte dcbz even on 64-bit machines
5008 bnelr++ ; return if another bit remains set
5010 neg r3,r3 ; indicate we just returned the last bit
5014 rlwinm r7,r5,1,31,31 ; move bit 0 of 2nd word to bit 31
5015 and. r0,r4,r7 ; is the 2-bit field that spans the 2 words free?
5017 rlwinm r4,r4,0,0,30 ; yes, turn off bit 31 of 1st word
5018 rlwinm r5,r5,0,1,31 ; turn off bit 0 of 2nd word
5025 ; It is done here because we may need to be 64-bit to do it.
5043 bt++ pf64Bitb,hhiSF ; skip if 64-bit (only they take the hint)
5067 rldimi r0,r8,63,MSR_SF_BIT ; Set SF bit (bit 0)
5112 bt++ pf64Bitb,hstSF ; skip if 64-bit (only they take the hint)
5158 ; 64-bit version
5177 rldicr r7,r7,0,35 ; Clear the valid bit and the rest
5213 ; Note that we transform the addr64_t (long long) parameters into single 64-bit values.
5229 ; but I just wanted to see if I could write this to work on both 32- and 64-bit
5234 ; Here we enter with va[0:31] in r6[0:31] (or r6[32:63] on 64-bit machines)
5235 ; and va[32:63] in r7[0:31] (or r7[32:63] on 64-bit machines)
5237 rlwinm r4,r4,0,1,0 ; Copy seg[0:31] into r4[0;31] - no-op for 32-bit
5243 rlwinm r8,r8,0,1,0 ; Dup low part into high (does nothing on 32-bit machines)
5246 rlwimi r8,r7,0,0,31 ; Join va[0:17] with va[18:35] (just like mr on 32-bit machines)
5250 ; at the top for 64-bit but we will clean
5252 rlwimi r4,r5,0,0,31 ; Copy seg[32:63] into r4[32:63] - just like mr for 32-bit
5257 ; va[18:35] shifted into r8[0:17], zeros elsewhere on 32-bit machines
5264 ; 0 8 6 4 2 0 8 6 3 - for 64-bit machines
5268 ; 0 0 1 2 3 - for 32-bit machines
5272 ; 0 8 6 4 2 0 8 6 3 - for 64-bit machines
5276 ; 0 0 1 2 3 - for 32-bit machines
5280 ; 0 8 6 4 2 0 8 6 3 - for 64-bit machines
5284 ; 0 0 1 2 3 - for 32-bit machines
5290 bf-- pf64Bitb,hms32bit ; Skip out if 32-bit...
5292 li r0,1 ; Prepare to set bit 0 (also to clear EE)
5295 mtmsrd r0,1 ; Set only the EE bit to 0
5296 rlwinm r6,r6,0,MSR_EE_BIT,MSR_EE_BIT ; See if EE bit is on
5299 rldimi r2,r0,63,0 ; Get bit 64-bit turned on
5300 or r11,r11,r6 ; Turn on the EE bit if it was on
5301 mtmsrd r2 ; Make sure translation and EE are off and 64-bit is on
5302 isync ; Hang out a bit
5305 sldi r9,r9,9 ; Position the key and noex bit
5316 oris r4,r4,0x0800 ; Turn on the valid bit in ESID
5328 rldicr r3,r3,0,35 ; Clear the valid bit and the rest
5341 srd r0,r0,r2 ; Set bit mask for allocation
5359 lis r0,0x8000 ; Set bit 0
5360 rlwimi r8,r9,28,1,3 ; Insert the keys and N bit
5361 srw r0,r0,r2 ; Get bit corresponding to SR
5389 bf-- pf64Bitb,hbs32bit ; Skip out if 32-bit...
5391 li r0,1 ; Prepare to set bit 0 (also to clear EE)
5394 mtmsrd r0,1 ; Set only the EE bit to 0
5395 rlwinm r6,r6,0,MSR_EE_BIT,MSR_EE_BIT ; See if EE bit is on
5398 rldimi r2,r0,63,0 ; Get bit 64-bit turned on
5399 or r11,r11,r6 ; Turn on the EE bit if it was on
5400 mtmsrd r2 ; Make sure translation and EE are off and 64-bit is on
5401 isync ; Hang out a bit
5428 hbsrupt: andc r4,r4,r2 ; Clear the valid bit for this segment
5479 ; If we go to the kernel it is set to 0, otherwise it follows the bit
5490 rlwinm r2,r3,MSR_PR_BIT+1,31,31 ; Isolate the problem mode bit
5491 rlwinm r3,r3,MSR_RI_BIT+1,31,31 ; Isolate the recoverable interrupt bit
5523 ori r16,r15,lo16(pmapCCtlLck) ; Set lock bit
5533 bf-- pf64Bitb,ssg32Enter ; If 32-bit, jump into it...
5551 ; This is the 32-bit address space switch code.
5574 andc r11,r11,r2 ; Clear the bit
5581 rlwinm r8,r7,19,1,3 ; Insert the keys and N bit
5604 srw r22,r0,r18 ; Get the mask bit
5620 ; This is the 64-bit address space switch code.
5636 andc r11,r11,r16 ; Clear the bit
5641 oris r5,r5,0x0800 ; Turn on the valid bit
5663 ; enter 64-bit mode if applicable.
5666 ; and CR6 set up so we can do easy branches for 64-bit
5683 li r2,1 ; Prepare for 64 bit
5686 bt++ pf64Bitb,msuSF ; skip if 64-bit (only they take the hint)
5694 msuSF: rldimi r0,r2,63,MSR_SF_BIT ; set SF bit (bit 0)
5695 mtmsrd r0 ; set 64-bit mode, turn off EE, DR, and IR
5715 ; r3 : address of pmap, 32-bit kernel virtual address
5751 bt++ pf64Bitb,gra64Salt ; Test for 64-bit machine
5753 lwz r9,pmapvr+4(r3) ; Get 32-bit virt<->real conversion salt
5757 ld r9,pmapvr(r3) ; Get 64-bit virt<->real conversion salt
5759 graStart: bl EXT(mapSetUp) ; Disable 'rupts, translation, enter 64-bit mode
5777 bt++ pf64Bitb,gra64Page ; Separate handling for 64-bit
5802 bt++ pf64Bitb,graDscon64 ; Handle 64-bit disconnect separately
5811 b graFreePTE ; Join 64-bit path to release the PTE
5816 lis r0,0x8000 ; Prepare free bit for this slot
5817 srw r0,r0,r2 ; Position free bit
5832 bt++ pf64Bitb,graRemove64 ; Use 64-bit version on 64-bit machine
5835 rlwinm. r9,r9,0,~ppFlags ; Remove flags, yielding 32-bit physical chain pointer
5861 andc. r9,r9,r7 ; Remove flags, yielding 64-bit physical chain pointer
5901 bt++ pf64Bitb,graRtn64 ; Handle 64-bit separately
5905 graRtn64: mtmsrd r30 ; Restore 'rupts, translation, 32-bit mode
5935 ; r3 : address of guest pmap, 32-bit kernel virtual address
5979 bt++ pf64Bitb,grl64Salt ; Test for 64-bit machine
5981 lwz r9,pmapvr+4(r3) ; Get 32-bit virt<->real conversion salt
5985 ld r9,pmapvr(r3) ; Get 64-bit virt<->real conversion salt
5988 grlStart: bl EXT(mapSetUp) ; Disable 'rupts, translation, enter 64-bit mode
6018 bt++ pf64Bitb,grl64Page ; Separate handling for 64-bit
6025 grlLoop: cntlzw r11,r23 ; Get next active bit lit in map word
6027 lis r12,0x8000 ; Prepare mask to reset bit
6028 srw r12,r12,r11 ; Position mask bit
6029 andc r23,r23,r12 ; Reset lit bit
6032 slwi r31,r11,GV_SLOT_SZ_LG2 ; Get slot offset in slot band from lit bit number
6039 rlwinm r5,r3,0,mpgGlobal ; Extract global bit
6043 andc r22,r22,r12 ; Reset active bit corresponding to this mapping
6047 bt++ pf64Bitb,grlDscon64 ; Handle 64-bit disconnect separately
6056 b grlFreePTE ; Join 64-bit path to release the PTE
6061 lis r0,0x8000 ; Prepare free bit for this slot
6062 srw r0,r0,r2 ; Position free bit
6074 bt++ pf64Bitb,grlRtn64 ; Handle 64-bit separately
6078 grlRtn64: mtmsrd r30 ; Restore 'rupts, translation, 32-bit mode
6106 ; r3 : address of host pmap, 32-bit kernel virtual address
6107 ; r4 : address of guest pmap, 32-bit kernel virtual address
6155 bt++ pf64Bitb,grs64Salt ; Handle 64-bit machine separately
6157 lwz r27,pmapvr+4(r3) ; Get 32-bit virt<->real host pmap conversion salt
6158 lwz r28,pmapvr+4(r4) ; Get 32-bit virt<->real guest pmap conversion salt
6170 grs64Salt: rldimi r29,r5,32,0 ; Insert high-order 32 bits of 64-bit host vaddr
6171 rldimi r30,r7,32,0 ; Insert high-order 32 bits of 64-bit guest vaddr
6173 ld r27,pmapvr(r3) ; Get 64-bit virt<->real host pmap conversion salt
6174 ld r28,pmapvr(r4) ; Get 64-bit virt<->real guest pmap conversion salt
6187 bl EXT(mapSetUp) ; Disable 'rupts, translation, maybe enter 64-bit mode
6195 bt++ pf64Bitb,grs64Search ; Test for 64-bit machine
6267 bt++ pf64Bitb,grsDscon64 ; Handle 64-bit disconnect separately
6276 b grsFreePTE ; Join 64-bit path to release the PTE
6281 lis r0,0x8000 ; Prepare free bit for this slot
6282 srw r0,r0,r2 ; Position free bit
6309 bt++ pf64Bitb,grsPFnd64 ; 64-bit version of physent chain search
6365 bt++ pf64Bitb,grsRemove64 ; Use 64-bit version on 64-bit machine
6368 rlwinm. r9,r9,0,~ppFlags ; Remove flags, yielding 32-bit physical chain pointer
6394 andc. r9,r9,r7 ; Remove flags, yielding 64-bit physical chain pointer
6431 bt++ pf64Bitb,grsRtn64 ; Handle 64-bit separately
6435 grsRtn64: mtmsrd r25 ; Restore 'rupts, translation, 32-bit mode
6471 ; r3 : address of host pmap, 32-bit kernel virtual address
6472 ; r4 : address of guest pmap, 32-bit kernel virtual address
6476 ; r8 : physical address, 32-bit page number
6486 ; r29 : physical address, 32-bit 4k-page number
6524 bt++ pf64Bitb,gad64Salt ; Test for 64-bit machine
6526 lwz r27,pmapvr+4(r3) ; Get 32-bit virt<->real host pmap conversion salt
6527 lwz r28,pmapvr+4(r4) ; Get 32-bit virt<->real guest pmap conversion salt
6540 ld r27,pmapvr(r3) ; Get 64-bit virt<->real host pmap conversion salt
6541 ld r28,pmapvr(r4) ; Get 64-bit virt<->real guest pmap conversion salt
6554 bl EXT(mapSetUp) ; Disable 'rupts, translation, maybe enter 64-bit mode
6563 bt++ pf64Bitb,gad64Search ; Test for 64-bit machine
6681 bt++ pf64Bitb,gadDscon64 ; Handle 64-bit disconnect separately
6690 b gadFreePTE ; Join 64-bit path to release the PTE
6695 lis r0,0x8000 ; Prepare free bit for this slot
6696 srw r0,r0,r2 ; Position free bit
6717 bt++ pf64Bitb,gadRemove64 ; Use 64-bit version on 64-bit machine
6720 rlwinm. r9,r9,0,~ppFlags ; Remove flags, yielding 32-bit physical chain pointer
6745 andc. r9,r9,r7 ; Remove flags, yielding 64-bit physical chain pointer
6778 bt++ pf64Bitb,gadVA64 ; Use 64-bit version on 64-bit machine
6788 bt++ pf64Bitb,gadChain64 ; Use 64-bit version on 64-bit machine
6813 bt++ pf64Bitb,gadRtn64 ; Handle 64-bit separately
6817 gadRtn64: mtmsrd r25 ; Restore 'rupts, translation, 32-bit mode
6849 ; r3 : address of host pmap, 32-bit kernel virtual address
6850 ; r4 : address of guest pmap, 32-bit kernel virtual address
6888 bt++ pf64Bitb,gsu64Salt ; Test for 64-bit machine
6891 lwz r27,pmapvr+4(r3) ; Get 32-bit virt<->real host pmap conversion salt
6892 lwz r28,pmapvr+4(r4) ; Get 32-bit virt<->real guest pmap conversion salt
6903 gsu64Salt: rldimi r30,r5,32,0 ; Insert high-order 32 bits of 64-bit guest vaddr
6905 ld r27,pmapvr(r3) ; Get 64-bit virt<->real host pmap conversion salt
6906 ld r28,pmapvr(r4) ; Get 64-bit virt<->real guest pmap conversion salt
6919 bl EXT(mapSetUp) ; Disable 'rupts, translation, maybe enter 64-bit mode
6927 bt++ pf64Bitb,gsu64Search ; Test for 64-bit machine
6996 bt++ pf64Bitb,gsuDscon64 ; Handle 64-bit disconnect separately
7005 b gsuFreePTE ; Join 64-bit path to release the PTE
7010 lis r0,0x8000 ; Prepare free bit for this slot
7011 srw r0,r0,r2 ; Position free bit
7028 bt++ pf64Bitb,gsuRtn64 ; Handle 64-bit separately
7032 gsuRtn64: mtmsrd r29 ; Restore 'rupts, translation, 32-bit mode
7050 ; and change bit, optionally�resetting them.
7053 ; r3 : address of host pmap, 32-bit kernel virtual address
7054 ; r4 : address of guest pmap, 32-bit kernel virtual address
7098 bt++ pf64Bitb,gtd64Salt ; Test for 64-bit machine
7101 lwz r27,pmapvr+4(r3) ; Get 32-bit virt<->real host pmap conversion salt
7102 lwz r28,pmapvr+4(r4) ; Get 32-bit virt<->real guest pmap conversion salt
7114 gtd64Salt: rldimi r30,r5,32,0 ; Insert high-order 32 bits of 64-bit guest vaddr
7116 ld r27,pmapvr(r3) ; Get 64-bit virt<->real host pmap conversion salt
7117 ld r28,pmapvr(r4) ; Get 64-bit virt<->real guest pmap conversion salt
7131 bl EXT(mapSetUp) ; Disable 'rupts, translation, maybe enter 64-bit mode
7139 bt++ pf64Bitb,gtd64Search ; Test for 64-bit machine
7208 bt++ pf64Bitb,gtdDo64 ; Split for 64 bit
7271 bt++ pf64Bitb,gtdR64 ; Test for 64-bit machine
7309 ; r3 : address of guest pmap, 32-bit kernel virtual address
7352 bt++ pf64Bitb,gth64Salt ; Test for 64-bit machine
7355 lwz r28,pmapvr+4(r3) ; Get 32-bit virt<->real guest pmap conversion salt
7368 gth64Salt: rldimi r30,r4,32,0 ; Insert high-order 32 bits of 64-bit guest vaddr
7370 ld r28,pmapvr(r3) ; Get 64-bit virt<->real guest pmap conversion salt
7383 bl EXT(mapSetUp) ; Disable 'rupts, translation, maybe enter 64-bit mode
7391 bt++ pf64Bitb,gth64Search ; Test for 64-bit machine
7464 bt++ pf64Bitb,gthPFnd64 ; 64-bit version of physent chain search
7509 li r3,-1 ; Return 64-bit -1
7511 bt++ pf64Bitb,gthEpi64 ; Take 64-bit exit
7512 b gthEpi32 ; Take 32-bit exit
7520 bt++ pf64Bitb,gthR64 ; Test for 64-bit machine
7561 ; r3 : address of guest pmap, 32-bit kernel virtual address
7564 ; r6 : 32 byte copy area, 32-bit kernel virtual address
7604 bt++ pf64Bitb,gfm64Salt ; Test for 64-bit machine
7607 lwz r28,pmapvr+4(r3) ; Get 32-bit virt<->real guest pmap conversion salt
7620 gfm64Salt: rldimi r30,r4,32,0 ; Insert high-order 32 bits of 64-bit guest vaddr
7622 ld r28,pmapvr(r3) ; Get 64-bit virt<->real guest pmap conversion salt
7635 bl EXT(mapSetUp) ; Disable 'rupts, translation, maybe enter 64-bit mode
7643 bt++ pf64Bitb,gfm64Search ; Test for 64-bit machine
7725 bt++ pf64Bitb,gfmEpi64 ; Test for 64-bit machine
7765 bt++ pf64Bitb,gfmEpi64 ; Take 64-bit exit
7766 b gfmEpi32 ; Take 32-bit exit
7776 ; r3 : address of guest pmap, 32-bit kernel virtual address
7817 bt++ pf64Bitb,gcp64Salt ; Handle 64-bit machine separately
7820 lwz r28,pmapvr+4(r3) ; Get 32-bit virt<->real guest pmap conversion salt
7832 gcp64Salt: rldimi r30,r4,32,0 ; Insert high-order 32 bits of 64-bit guest vaddr
7835 ld r28,pmapvr(r3) ; Get 64-bit virt<->real guest pmap conversion salt
7847 bl EXT(mapSetUp) ; Disable 'rupts, translation, maybe enter 64-bit mode
7855 bt++ pf64Bitb,gcp64Search ; Test for 64-bit machine
7924 bt++ pf64Bitb,gcpDscon64 ; Handle 64-bit disconnect separately
7933 b gcpFreePTE ; Join 64-bit path to release the PTE
7938 lis r0,0x8000 ; Prepare free bit for this slot
7939 srw r0,r0,r2 ; Position free bit
7957 bt++ pf64Bitb,gcpRtn64 ; Handle 64-bit separately
7961 gcpRtn64: mtmsrd r25 ; Restore 'rupts, translation, 32-bit mode
8022 oris r0,r2,0x8000 ; Set the lock bit
8044 ; an entry. The sub-tag is a 16 entry 4 bit array that contains the low order 4 bits
8045 ; of the ESID, bits 32:36 of the effective for 64-bit and 0:3 for 32-bit. The cache
8046 ; entry contains the full 36 bit ESID.
8075 ori r0,r11,lo16(pmapCCtlLck) ; Turn on the lock bit
8127 srw r2,r0,r5 ; Get validity mask bit
8129 andc r6,r6,r2 ; Clear the validity bit we just tried
8182 rlwinm r3,r0,0,0,30 ; Clear the valid bit
8213 ; 64-bit version of mapMergeRC
8237 rlwinm r3,r0,0,0,30 ; Clear the valid bit
8241 b mMNmerge ; Join the common 32-64-bit code...
8283 rlwinm r3,r0,0,0,30 ; Clear the valid bit
8288 rlwinm r0,r4,0,1,31 ; Clear the valid bit
8346 ; 64-bit version
8370 rlwinm r3,r0,0,0,30 ; Clear the valid bit
8375 rldicr r0,r4,0,62 ; Clear the valid bit
8404 b mINmerge ; Join the common 32-64-bit code...
8426 ori r0,r6,PCAlock ; Set the lock bit
8453 ; The PTEG allocation controls are a bit map of the state of the PTEG.
8498 rlwinm r4,r4,0,29,31 ; Isolate bit position
8499 rlwimi r11,r11,8,16,23 ; Get set to march a 1 back into top of 8 bit rotate
8504 addi r0,r8,0x7F00 ; Push autogen flag to bit 16
8506 addis r8,r8,0xFF00 ; Push in use to bit 0 and invert
8507 or r6,r6,r2 ; Add in the new autogen bit
8620 b sxlkXWaiu ; Hang around a bit more...
8647 b sxlkSWaiu ; Hang around a bit more...
8680 rlwinm r4,r4,0,1,0 ; Copy fill to top of 64-bit register
8694 bt++ pf64Bitb,fpSF1 ; skip if 64-bit (only they take the hint)
8722 sldi r2,r2,63 ; Get 64-bit bit
8723 or r0,r0,r2 ; Turn on 64-bit