Lines Matching defs:mmcr0_reg
168 ppc32_mmcr0_reg_t mmcr0_reg;
170 mmcr0_reg.value = 0;
171 mmcr0_reg.field.disable_counters_always = TRUE;
172 mmcr0_reg.field.disable_counters_supervisor = TRUE; /* no choice */
173 sv->save_mmcr0 = mmcr0_reg.value;
178 ppc64_mmcr0_reg_t mmcr0_reg;
180 mmcr0_reg.value = 0;
181 mmcr0_reg.field.disable_counters_always = TRUE;
182 mmcr0_reg.field.disable_counters_supervisor = TRUE; /* no choice */
183 sv->save_mmcr0 = mmcr0_reg.value;
325 ppc32_mmcr0_reg_t mmcr0_reg;
326 mmcr0_reg.value = sv->save_mmcr0;
327 mmcr0_reg.field.disable_counters_always = FALSE;
329 mmcr0_reg.field.on_pmi_stop_counting = FALSE;
330 mmcr0_reg.field.enable_pmi = FALSE;
331 mmcr0_reg.field.enable_pmi_on_pmc1 = FALSE;
332 mmcr0_reg.field.enable_pmi_on_pmcn = FALSE;
333 sv->save_mmcr0 = mmcr0_reg.value;
338 ppc32_mmcr0_reg_t mmcr0_reg;
339 mmcr0_reg.value = sv->save_mmcr0;
340 mmcr0_reg.field.disable_counters_always = FALSE;
341 mmcr0_reg.field.on_pmi_stop_counting = TRUE;
342 mmcr0_reg.field.enable_pmi = TRUE;
343 mmcr0_reg.field.enable_pmi_on_pmc1 = TRUE;
344 mmcr0_reg.field.enable_pmi_on_pmcn = TRUE;
345 sv->save_mmcr0 = mmcr0_reg.value;
350 ppc64_mmcr0_reg_t mmcr0_reg;
351 mmcr0_reg.value = sv->save_mmcr0;
352 mmcr0_reg.field.disable_counters_always = FALSE;
353 mmcr0_reg.field.on_pmi_stop_counting = TRUE;
354 mmcr0_reg.field.enable_pmi = TRUE;
355 mmcr0_reg.field.enable_pmi_on_pmc1 = TRUE;
356 mmcr0_reg.field.enable_pmi_on_pmcn = TRUE;
357 sv->save_mmcr0 = mmcr0_reg.value;
383 ppc32_mmcr0_reg_t mmcr0_reg;
384 mmcr0_reg.value = sv->save_mmcr0;
385 mmcr0_reg.field.disable_counters_always = TRUE;
386 sv->save_mmcr0 = mmcr0_reg.value;
391 ppc64_mmcr0_reg_t mmcr0_reg;
392 mmcr0_reg.value = sv->save_mmcr0;
393 mmcr0_reg.field.disable_counters_always = TRUE;
394 sv->save_mmcr0 = mmcr0_reg.value;
423 ppc32_mmcr0_reg_t mmcr0_reg;
426 mmcr0_reg.value = sv->save_mmcr0;
431 mmcr0_reg.field.pmc1_event = event;
432 sv->save_mmcr0 = mmcr0_reg.value;
435 mmcr0_reg.field.pmc2_event = event;
436 sv->save_mmcr0 = mmcr0_reg.value;
454 ppc32_mmcr0_reg_t mmcr0_reg;
457 mmcr0_reg.value = sv->save_mmcr0;
462 mmcr0_reg.field.pmc1_event = event;
463 sv->save_mmcr0 = mmcr0_reg.value;
466 mmcr0_reg.field.pmc2_event = event;
467 sv->save_mmcr0 = mmcr0_reg.value;
493 ppc64_mmcr0_reg_t mmcr0_reg;
496 mmcr0_reg.value = sv->save_mmcr0;
501 mmcr0_reg.field.pmc1_event = event;
502 sv->save_mmcr0 = mmcr0_reg.value;
505 mmcr0_reg.field.pmc2_event = event;
506 sv->save_mmcr0 = mmcr0_reg.value;
617 ppc32_mmcr0_reg_t mmcr0_reg;
619 mmcr0_reg.value = sv->save_mmcr0;
628 mmcr0_reg.field.threshold_value = threshold;
630 sv->save_mmcr0 = mmcr0_reg.value;
637 ppc32_mmcr0_reg_t mmcr0_reg;
640 mmcr0_reg.value = sv->save_mmcr0;
669 mmcr0_reg.field.threshold_value = threshold;
671 sv->save_mmcr0 = mmcr0_reg.value;
678 ppc64_mmcr0_reg_t mmcr0_reg;
680 mmcr0_reg.value = sv->save_mmcr0;
689 mmcr0_reg.field.threshold_value = threshold;
691 sv->save_mmcr0 = mmcr0_reg.value;
717 ppc32_mmcr0_reg_t mmcr0_reg;
719 mmcr0_reg.value = sv->save_mmcr0;
725 mmcr0_reg.field.timebase_bit_selector = tbsel;
730 sv->save_mmcr0 = mmcr0_reg.value;
735 ppc64_mmcr0_reg_t mmcr0_reg;
737 mmcr0_reg.value = sv->save_mmcr0;
743 mmcr0_reg.field.timebase_bit_selector = tbsel;
748 sv->save_mmcr0 = mmcr0_reg.value;
932 ppc32_mmcr0_reg_t mmcr0_reg;
934 mmcr0_reg.value = thread->machine.pcb->save_mmcr0;
935 mmcr0_reg.field.disable_counters_always = FALSE;
936 mmcr0_reg.field.enable_pmi = TRUE;
937 thread->machine.pcb->save_mmcr0 = mmcr0_reg.value;
943 ppc64_mmcr0_reg_t mmcr0_reg;
945 mmcr0_reg.value = thread->machine.pcb->save_mmcr0;
946 mmcr0_reg.field.disable_counters_always = FALSE;
947 mmcr0_reg.field.enable_pmi = TRUE;
948 thread->machine.pcb->save_mmcr0 = mmcr0_reg.value;