Lines Matching refs:on
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
47 * Load the context for the first thread to run on a
121 * savesrr1 is set to uninterruptible with translation on
133 mr. r0,r0 ; (DEBUG/TRACE) on the interrupt
161 mr. r2,r2 ; Any tracing going on?
322 b EXT(exception_exit) ; Blocking on continuation, toss old context...
330 * with translation on. If we could, this should be done in lowmem_vectors
331 * before translation is turned on. But we can't, dang it!
333 * switch_in() runs with DR on and IR off
356 lwz r10,ACT_MACT_PCB(r9) ; Get the top PCB on the old thread
358 stw r3,ACT_MACT_PCB(r9) ; Put the new one on top
359 stw r10,SAVprev+4(r3) ; Chain on the old one
423 lwz r9,FPUcpu(r3) ; Get the cpu that context was last on
428 bne-- fsret ; Facility not last used on this processor...
434 ; we are trying to save it on out. Then we will give it the final check.
468 lwz r5,FPUcpu(r12) ; Get the cpu that context was last on
504 fsret: mtmsr r0 ; Put interrupts on if they were and floating point off
518 STRINGD "fpu_save: timeout on sync lock (0x%08X), value = 0x%08X\n\000"
528 * This code is run in virtual address mode on with interrupts off.
531 * point facility turned on.
586 lwz r18,FPUcpu(r22) ; Get the last CPU we ran on
589 cmplw r18,r16 ; Make sure we are on the right processor
593 bne-- fsnosave ; No, not on the same processor...
608 ; Note it turns out that on a G5, the following load has about a 50-50 chance of
619 ; we are trying to save it on out
653 ; A new context can not be pushed on top of us, but it can be popped. The
662 lwz r18,FPUcpu(r22) ; Get the last CPU we ran on again
756 lwz r19,FPUcpu(r29) ; Get the last CPU we ran on
818 // are executed on a 128-byte machine, but that is better than a mispredicted branch.
948 ; is still live. Essentially, all we are doing is turning on the facility. It may have
1022 rlwinm. r8,r9,0,MSR_FP_BIT,MSR_FP_BIT ; Are floats on right now?
1034 ; Note that at this point, since floats are on, we are the owner
1035 ; of live state on this processor
1046 tlfnotours: lwz r11,FPUcpu(r3) ; Get the cpu on which we last loaded context
1078 * to the VRSAVE register. It is loaded based on VRSAVE anded with
1137 lwz r9,VMXcpu(r12) ; Get the cpu that context was last on
1148 ; we are trying to save it on out. Then we will give it the final check.
1183 lwz r5,VMXcpu(r12) ; Get the cpu that context was last on
1254 vsret: mtmsr r0 ; Put interrupts on if they were and vector off
1269 * This code is run with virtual address mode on and interrupts off.
1272 * facility turned on.
1328 lwz r18,VMXcpu(r22) ; Get the last CPU we ran on
1333 cmplw r18,r16 ; Make sure we are on the right processor
1337 bne-- vswnosave ; No, not on the same processor...
1352 ; we are trying to save it on out
1386 ; A new context can not be pushed on top of us, but it can be popped. The
1395 lwz r18,VMXcpu(r22) ; Get the last CPU we ran on again
1514 lwz r19,VMXcpu(r29) ; Get the last CPU we ran on
1580 bl vr_load ; load VRs from save area based on vrsave in r10
1660 ; is still live. Essentially, all we are doing is turning on the faility. It may have
1703 rlwinm. r8,r9,0,MSR_VEC_BIT,MSR_VEC_BIT ; Are vectors on right now?
1715 ; Note that at this point, since vecs are on, we are the owner
1716 ; of live state on this processor
1724 vspltish v1,1 ; Turn on the non-Java bit and saturate
1725 vspltisw v0,1 ; Turn on the saturate bit
1730 tlvnotours: lwz r11,VMXcpu(r3) ; Get the cpu on which we last loaded context
1773 lwz r11,VMXcpu(r3) ; Get the cpu on which we last loaded context
1852 // Store the FPRs on a 128-byte machine.
1890 // Store FPRs on a 32-byte machine.
1970 ; Save vectors on a 128-byte linesize processor. We save all or none of the 8 registers in each of
2041 ; Save vectors on a 32-byte linesize processor. We save in 16 groups of 2: we either save both
2042 ; or neither in each group. This cuts down on conditional branches.
2047 mtcrf 0xFF,r8 ; set CR bits so we can branch on them