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74 stw r10,spcFlags(r6) /* Set per_proc copy of the special flags */
118 * R7 = high order physical address of savearea for full switch
155 stw r6,ppUMWmp+mpNestReloc(r12) ; Save top part of physical address
156 stw r2,ppUMWmp+mpNestReloc+4(r12) ; Save bottom part of physical address
159 stw r7,spcFlags(r12) ; Set per_proc copy of the special flags
162 lwz r11,SAVprev+4(r8) ; Get the previous of the switchee savearea
168 sc ; Cut trace entry of context switch
171 lwz r10,FPUowner(r12) ; Grab the owner of the FPU
172 lwz r9,VMXowner(r12) ; Grab the owner of the vector
201 lwz r5,SAVprev+4(r10) ; Get the previous of this savearea
208 rlwinm r3,r10,0,0,19 ; Move back to start of page
249 lwz r5,SAVprev+4(r10) ; Get the previous of this savearea
255 rlwinm r3,r10,0,0,19 ; Move back to start of page
276 lis r9,hi16(EXT(switch_in)) ; Get top of switch in routine
279 ; Note that the low-level code requires the R7 contain the high order half of the savearea's
284 ori r9,r9,lo16(EXT(switch_in)) ; Bottom half of switch in
289 lis r0,hi16(SwitchContextCall) /* Top part of switch context */
291 ori r0,r0,lo16(SwitchContextCall) /* Bottom part of switch context */
294 xor r3,r11,r8 /* Get the physical address of the new context save area */
308 ; killing off the old context of the new guy so we need to pop off
311 ; Note that we do the same kind of thing a chkfac in hw_exceptions.s
320 mr r3,r8 ; Pass in the virtual address of savearea
477 lwz r8,SAVlevel(r7) ; Get the level of this savearea
546 lis r3,hi16(EXT(fpu_trap_count)) ; Get address of FP trap counter
547 ori r3,r3,lo16(EXT(fpu_trap_count)) ; Get address of FP trap counter
565 lwz r29,curctx(r17) ; Grab the current context anchor of the current thread
608 ; Note it turns out that on a G5, the following load has about a 50-50 chance of
653 ; A new context can not be pushed on top of us, but it can be popped. The
657 ; It should be very rare that any of the context stuff changes across the lock.
674 lwz r11,SAVlevel(r30) ; Get the level of top saved context
720 ; of some thread! Just imagine what would happen if they could! Why, nothing
755 lwz r15,ACT_MACT_PCB(r17) ; Get the current level of the "new" one
757 lwz r14,FPUsave(r29) ; Point to the top of the "new" context stack
784 srawi r11,r11,31 ; Get a 0 if equal or -1 of not
799 lwz r0,SAVlevel(r14) ; Get the level of first facility savearea
870 fsenable: lwz r8,savesrr1+4(r25) ; Get the msr of the interrupted guy
877 stw r8,savesrr1+4(r25) ; Set the msr of the interrupted guy
878 mr r3,r25 ; Pass the virtual addres of savearea
970 lwz r11,SAVlevel(r30) ; Get the level of top saved context
1035 ; of live state on this processor
1059 srawi r8,r8,31 ; Get a 0 if equal or -1 of not
1074 * There are two indications of saved VRs: the VRSAVE register and the vrvalid
1080 * don't want to load any registers we don't have a copy of, we want to set them
1228 mr. r12,r12 ; See if we were disowned while away. Very, very small chance of it...
1287 lis r3,hi16(EXT(vec_trap_count)) ; Get address of vector trap counter
1288 ori r3,r3,lo16(EXT(vec_trap_count)) ; Get address of vector trap counter
1306 lwz r29,curctx(r17) ; Grab the current context anchor of the current thread
1386 ; A new context can not be pushed on top of us, but it can be popped. The
1390 ; It should be very rare that any of the context stuff changes across the lock.
1408 lwz r11,SAVlevel(r30) ; Get the level of top saved context
1468 ; of some thread! Just imagine what would happen if they could! Why, nothing
1512 lwz r15,ACT_MACT_PCB(r17) ; Get the current level of the "new" one
1516 lwz r14,VMXsave(r29) ; Point to the top of the "new" context stack
1549 srawi r11,r11,31 ; Get a 0 if equal or -1 of not
1563 lwz r0,SAVlevel(r14) ; Get the level of first facility savearea
1588 vrenable: lwz r8,savesrr1+4(r25) ; Get the msr of the interrupted guy
1595 stw r8,savesrr1+4(r25) ; Set the msr of the interrupted guy
1596 mr r3,r25 ; Pass virtual address of the savearea
1677 lwz r11,SAVlevel(r30) ; Get the level of top saved context
1716 ; of live state on this processor
1744 srawi r8,r8,31 ; Get a 0 if equal or -1 of not
1786 srawi r8,r8,31 ; Get a 0 if equal or -1 of not
1793 lwz r8,SAVlevel(r9) ; Get the level of the savearea
1950 // unnecessary cache blocks, we either save all or none of the VRs in a block. We have separate paths
1970 ; Save vectors on a 128-byte linesize processor. We save all or none of the 8 registers in each of
1973 slwi r7,r8,2 ; shift groups-of-2 over by 2
1975 or r8,r7,r8 ; show if any in group of 4 are in use
1977 slwi r7,r8,4 ; shift groups-of-4 over by 4
1979 or r11,r7,r8 ; show if any in group of 8 are in use
1989 bf 0,vr_st64b ; skip if none of vr0-vr7 are in use
1990 la r11,savevr0(r3) ; get address of this group of registers in save area
2002 bf 8,vr_st64c ; skip if none of vr8-vr15 are in use
2003 la r11,savevr8(r3) ; get address of this group of registers in save area
2015 bf 16,vr_st64d ; skip if none of vr16-vr23 are in use
2016 la r11,savevr16(r3) ; get address of this group of registers in save area
2028 bflr 24 ; done if none of vr24-vr31 are in use
2029 la r11,savevr24(r3) ; get address of this group of registers in save area
2041 ; Save vectors on a 32-byte linesize processor. We save in 16 groups of 2: we either save both
2043 ; r8 = bitmask with bit n set (for even n) if either of that pair of VRs is in use
2051 la r11,savevr0(r3) ; get address of this group of registers in save area
2058 la r11,savevr2(r3) ; get address of this group of registers in save area
2065 la r11,savevr4(r3) ; get address of this group of registers in save area
2072 la r11,savevr6(r3) ; get address of this group of registers in save area
2079 la r11,savevr8(r3) ; get address of this group of registers in save area
2086 la r11,savevr10(r3) ; get address of this group of registers in save area
2093 la r11,savevr12(r3) ; get address of this group of registers in save area
2100 la r11,savevr14(r3) ; get address of this group of registers in save area
2107 la r11,savevr16(r3) ; get address of this group of registers in save area
2114 la r11,savevr18(r3) ; get address of this group of registers in save area
2121 la r11,savevr20(r3) ; get address of this group of registers in save area
2128 la r11,savevr22(r3) ; get address of this group of registers in save area
2135 la r11,savevr24(r3) ; get address of this group of registers in save area
2142 la r11,savevr26(r3) ; get address of this group of registers in save area
2149 la r11,savevr28(r3) ; get address of this group of registers in save area
2156 la r11,savevr30(r3) ; get address of this group of registers in save area
2168 // of "vr_store". Like it, we avoid touching unnecessary cache blocks and minimize conditional
2176 // r10 = vector of live regs to load (ie, savevrsave & savevrvalid, may be 0)
2200 li r5,0 ; initialize set of VRs to load
2201 la r11,savevr0(r3) ; get address of register file
2206 dcbt r4,r11 ; start prefetch of the line
2218 // Handle a processor with 128-byte cache lines. Four groups of 8 VRs.
2322 // Handle a processor with 32-byte cache lines. Sixteen groups of two VRs.