Lines Matching refs:is
81 * Switch from one thread to another. If a continuation is supplied, then
103 * See if a continuation is supplied, and skip state save if so.
120 * savesrr0 is set to go to switch_in
121 * savesrr1 is set to uninterruptible with translation on
140 cmpwi cr1,r4,0 ; Remeber if there is a continuation - used waaaay down below
184 bne++ cswnofloat ; Float is not ours...
189 bne++ cswnofloat ; Level not the same, this is not live...
230 cswnofloat: bne++ cr5,cswnovect ; Vector is not ours...
237 bne++ cswnovect ; Level not the same, this is not live...
280 ; physical address. This is hack city, but it is the way it is.
307 ; This is where we go when a continuation is set. We are actually
331 * before translation is turned on. But we can't, dang it!
377 * It is really not too cool to do this, but what the hey... Anyway,
378 * we turn fpus and vecs off before we leave., The oddity is that if you use fpus after this, the
379 * savearea containing the context just saved will go away. So, bottom line is
433 ; First, make sure that the live context block is not mucked with while
479 beq-- fsretlk ; The current level is already saved, bail out...
528 * This code is run in virtual address mode on with interrupts off.
535 * State is saved in savearea pointed to by R4.
581 mr. r22,r22 ; See if there is any live FP status
609 ; taking a segment exception in a system that is doing heavy file I/O. We
618 ; Make sure that the live context block is not mucked with while
671 bne-- fsnosavelk ; Something has changed, so this is not ours to save...
672 beq-- cr1,fsmstsave ; There is no context saved yet...
716 ; The context is all saved now and the facility is free.
721 ; would be safe! My God! It is terrifying!
723 ; Make sure that the live context block is not mucked with while
749 bne-- fsnsync0 ; Unfortunately, it is locked...
817 // Note this code is used both by 32- and 128-byte processors. This means six extra DCBTs
818 // are executed on a 128-byte machine, but that is better than a mispredicted branch.
948 ; is still live. Essentially, all we are doing is turning on the facility. It may have
983 ; Note that we need to choke in this code rather than panic because there is no
1011 ; This is intended to be called just before act_machine_sv_free tosses saveareas.
1070 * Altivec stuff is here. The techniques used are pretty identical to
1075 * mask. VRSAVE is set by the vector user and represents the VRs that they
1077 * are saved in the savearea. Whenever context is saved, it is saved according
1078 * to the VRSAVE register. It is loaded based on VRSAVE anded with
1079 * vrvalid (all other registers are splatted with 0s). This is done because we
1084 * It is really not too cool to do this, but what the hey... Anyway,
1086 * The oddity is that if you use vectors after this, the
1087 * savearea containing the context just saved will go away. So, bottom line is
1141 bne-- vsret ; Specified context is not live
1145 ; the VRSAVE is 0.
1147 ; First, make sure that the live context block is not mucked with while
1172 bne-- vssync0 ; No, it is unlocked...
1193 lwz r8,SAVlevel(r7) ; Get the level this savearea is for
1197 bne++ cr1,vsretlk ; VRsave is non-zero so we need to keep what is saved...
1219 vsneedone: beq-- cr1,vsclrlive ; VRSave is zero, go blow away the context...
1269 * This code is run with virtual address mode on and interrupts off.
1276 * State is saved in savearea pointed to by R4.
1323 mr. r22,r22 ; See if there is any live vector status
1351 ; Make sure that the live context block is not mucked with while
1405 bne-- vswnosavelk ; Something has changed, so this is not ours to save...
1406 beq-- cr1,vswmstsave ; There is no context saved yet...
1425 li r5,0 ; Assume this is the only one (which should be the ususal case)
1441 beq-- cr2,vswnosavelk ; The VRSave was 0, so there is nothing to save...
1464 ; The context is all saved now and the facility is free.
1469 ; would be safe! My God! It is terrifying!
1474 ; Make sure that the live context block is not mucked with while
1505 bne-- vswnsync0 ; Unfortunately, it is locked...
1660 ; is still live. Essentially, all we are doing is turning on the faility. It may have
1692 ; This is intended to be called just before act_machine_sv_free tosses saveareas.
1756 ; if the level is current. It also tosses the corresponding savearea if there is one.
1757 ; This function is primarily used whenever we detect a VRSave that is all zeros.
1770 cmplwi cr1,r9,0 ; Remember if there is a savearea
1792 beqlr++ cr1 ; Leave if there is no savearea
1839 // floating pt is enabled
1849 dcbz128 0,r11 ; establish 1st line no matter what linesize is
1948 // Store VRs into savearea, according to bits set in passed vrsave bitfield. This routine is used
2043 ; r8 = bitmask with bit n set (for even n) if either of that pair of VRs is in use
2050 bf 0,vr_st32b ; skip if neither VR in this pair is in use
2057 bf 2,vr_st32c ; skip if neither VR in this pair is in use
2064 bf 4,vr_st32d ; skip if neither VR in this pair is in use
2071 bf 6,vr_st32e ; skip if neither VR in this pair is in use
2078 bf 8,vr_st32f ; skip if neither VR in this pair is in use
2085 bf 10,vr_st32g ; skip if neither VR in this pair is in use
2092 bf 12,vr_st32h ; skip if neither VR in this pair is in use
2099 bf 14,vr_st32i ; skip if neither VR in this pair is in use
2106 bf 16,vr_st32j ; skip if neither VR in this pair is in use
2113 bf 18,vr_st32k ; skip if neither VR in this pair is in use
2120 bf 20,vr_st32l ; skip if neither VR in this pair is in use
2127 bf 22,vr_st32m ; skip if neither VR in this pair is in use
2134 bf 24,vr_st32n ; skip if neither VR in this pair is in use
2141 bf 26,vr_st32o ; skip if neither VR in this pair is in use
2148 bf 28,vr_st32p ; skip if neither VR in this pair is in use
2155 bflr 30 ; done if neither VR in this pair is in use
2167 // Load live VRs from a savearea, according to bits set in a passed vector. This is the reverse
2170 // in a cache line, we bug them. Note that this behavior is slightly different from earlier kernels,
2220 // r5 = 1st bit in each cacheline is 1 iff any reg in that line must be loaded
2227 mtcrf 0x20,r5 ; load CRs ona at a time, which is faster
2323 // r5 = 1st bit in each cacheline is 1 iff any reg in that line must be loaded
2331 vor v0,v31,v31 ; neither VR is live, so bug them both
2341 vor v2,v31,v31 ; neither VR is live, so bug them both
2351 vor v4,v31,v31 ; neither VR is live, so bug them both
2361 vor v6,v31,v31 ; neither VR is live, so bug them both
2371 vor v8,v31,v31 ; neither VR is live, so bug them both
2381 vor v10,v31,v31 ; neither VR is live, so bug them both
2391 vor v12,v31,v31 ; neither VR is live, so bug them both
2401 vor v14,v31,v31 ; neither VR is live, so bug them both
2411 vor v16,v31,v31 ; neither VR is live, so bug them both
2421 vor v18,v31,v31 ; neither VR is live, so bug them both
2431 vor v20,v31,v31 ; neither VR is live, so bug them both
2441 vor v22,v31,v31 ; neither VR is live, so bug them both
2451 vor v24,v31,v31 ; neither VR is live, so bug them both
2461 vor v26,v31,v31 ; neither VR is live, so bug them both
2471 vor v28,v31,v31 ; neither VR is live, so bug them both
2481 vor v30,v31,v31 ; neither VR is live, so bug them both