Lines Matching refs:all
18 * The Original Code and all software distributed under the License are
497 bl fp_store ; save all 32 FPRs in the save area at r3
597 ; Also check to see if all we are here just to re-enable the MSR
709 bl fp_store ; store all 32 FPRs
716 ; The context is all saved now and the facility is free.
912 fmr f1,f0 ; Do them all
943 b fsenable ; Finish setting it all up...
948 ; is still live. Essentially, all we are doing is turning on the facility. It may have
1079 * vrvalid (all other registers are splatted with 0s). This is done because we
1341 ; Also check to see if all we are here just to re-enable the MSR
1464 ; The context is all saved now and the facility is free.
1654 b vrenablelk ; Finish setting it all up...
1660 ; is still live. Essentially, all we are doing is turning on the faility. It may have
1757 ; This function is primarily used whenever we detect a VRSave that is all zeros.
1950 // unnecessary cache blocks, we either save all or none of the VRs in a block. We have separate paths
1959 // r4 - r11, all CRs.
1970 ; Save vectors on a 128-byte linesize processor. We save all or none of the 8 registers in each of
2169 // branches by loading all VRs from a cache line, if we have to load any. If we don't load the VRs
2171 // which would bug all VRs that aren't live.
2180 // r4 - r11, all CRs.
2208 or r5,r5,r9 ; we will load all these
2237 vor v0,v31,v31 ; no VR must be loaded, so bug them all
2259 vor v8,v31,v31 ; no VR must be loaded, so bug them all
2281 vor v16,v31,v31 ; no VR must be loaded, so bug them all
2303 vor v24,v31,v31 ; no VR must be loaded, so bug them all