Lines Matching refs:r8
48 * r8 = ptr to the 1st byte to store (16-byte aligned)
54 * r8 = ptr to next byte to store (still 16-byte aligned)
65 andi. r5,r8,0x10 // is ptr 32-byte aligned?
76 stvx v0,0,r8 // store another 16 bytes to align
77 addi r8,r8,16
83 dcba 0,r8 // pre-allocate first cache line (possibly nop'd)
89 dcba r6,r8 // zero 2nd cache line (possibly nop'd)
97 dcba r10,r8 // zero one 64-byte chunk ahead (possibly nop'd)
98 dcba r11,r8
99 stvx v0,0,r8
100 stvx v0,r5,r8
101 stvx v0,r6,r8
102 stvx v0,r9,r8
103 addi r8,r8,64
108 stvx v0,0,r8
109 stvx v0,r5,r8
110 stvx v0,r6,r8
111 stvx v0,r9,r8
112 addi r8,r8,64
121 stvx v0,0,r8
122 stvx v0,r5,r8
123 addi r8,r8,32