Lines Matching refs:r20
95 rlwinm r20,r10,16,22,31 ; Set rS/rD and rA
100 rlwimi r20,r10,14,15,16 ; Move bits 29 and 30 of instruction to 15 and 16 of DSISR
102 rlwimi r20,r10,8,17,17 ; Move bit 25 to bit 17
105 rlwimi r20,r10,3,18,21 ; Move bit 21-24 to bit 18-21
142 eFinishUp: stw r20,savedsisr(r13) ; Set the DSISR
225 aan64: lwz r20,savedsisr(r13) ; Get the DSISR
228 mtcrf 0x10,r20 ; Put instruction ID in CR for later
231 mtcrf 0x08,r20 ; Put instruction ID in CR for later
233 mtcrf 0x04,r20 ; Put instruction ID in CR for later
238 mr r26,r20 ; Save the DSISR
249 rlwinm r24,r20,3,24,28 ; Get displacement to register to update if update form
250 rlwimi r20,r20,24,28,28 ; Move load/store indication to the bottom of index
252 rlwimi r20,r20,26,27,27 ; Move single/double indication to just above the bottom
259 rlwimi r29,r20,0,22,28 ; Index into table based upon register||iDouble||iStore
1036 mr r20,r1 ; Save the DSISR
1041 stw r20,savedsisr(r13) ; Set the DSISR of failed access