Lines Matching refs:opcode
86 uint_t it_invalid64:1; /* opcode invalid in amd64 */
225 #define MODE_IMPLIED 3 /* constant value implied from opcode */
232 * "T" - means to Terminate indirections (this is the final opcode)
234 * "NS" - means "no suffix" which is the operand length suffix of the opcode
236 * "u" - means the opcode is invalid in IA32 but valid in amd64
237 * "x" - means the opcode is invalid in amd64, but not IA32
433 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
489 * Decode table for 0x0FC7 opcode
500 * Decode table for 0x0FC8 opcode -- 486 bswap instruction
1244 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */
1469 uint_t ss; /* scale-factor from opcode */
1661 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
1700 * returns non-zero for bad opcode
1715 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */
1724 uint_t opcode3; /* extra opcode bits usually from ModRM byte */
1772 * Get one opcode byte and check for zero padding that follows
1876 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
1934 * In amd64 bit mode, ARPL opcode is changed to MOVSXD
1941 * at this point we should have a correct (or invalid) opcode
2047 * At this point most instructions can format the opcode mnemonic
2132 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s)
2206 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83
2434 /* long seg reg from opcode */
2839 * byte (format Ib). The int 3 instruction (opcode 0xCC),
2841 * it is implied by the opcode. It must be converted
3058 isunsigned_op(char *opcode)
3068 where = opcode + strlen(opcode) - 1;
3069 while (where > opcode && *where != ' ')