Lines Matching defs:OS
65 void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
66 unsigned FeatureKeyValues(raw_ostream &OS);
67 unsigned CPUKeyValues(raw_ostream &OS);
76 void EmitStageAndOperandCycleData(raw_ostream &OS,
79 void EmitItineraries(raw_ostream &OS,
82 void EmitProcessorProp(raw_ostream &OS, const Record *R, const char *Name,
85 raw_ostream &OS);
92 void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
93 void EmitProcessorModels(raw_ostream &OS);
94 void EmitProcessorLookup(raw_ostream &OS);
95 void EmitSchedModelHelpers(std::string ClassName, raw_ostream &OS);
96 void EmitSchedModel(raw_ostream &OS);
97 void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
112 void SubtargetEmitter::Enumeration(raw_ostream &OS,
127 OS << "namespace " << Target << " {\n";
138 OS << " const uint64_t " << Def->getName() << " = 1ULL << " << i << ";\n";
142 OS << "enum {\n";
150 OS << " " << Def->getName();
153 if (isBits) OS << " = " << " 1ULL << " << i;
156 if (++i < N) OS << ",";
158 OS << "\n";
162 OS << "};\n";
165 OS << "}\n";
172 unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
183 OS << "// Sorted (by key) array of values for CPU features.\n"
200 OS << " { "
209 OS << "0ULL";
212 OS << Target << "::" << ImpliesList[j]->getName();
213 if (++j < M) OS << " | ";
217 OS << " }";
221 if ((i + 1) < N) OS << ",";
223 OS << "\n";
227 OS << "};\n";
236 unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
243 OS << "// Sorted (by key) array of values for CPU subtype.\n"
257 OS << " { "
262 OS << "0ULL";
265 OS << Target << "::" << FeatureList[j]->getName();
266 if (++j < M) OS << " | ";
271 OS << ", 0ULL }";
274 if (++i < N) OS << ",";
276 OS << "\n";
280 OS << "};\n";
376 EmitStageAndOperandCycleData(raw_ostream &OS,
395 OS << "\n// Functional units for \"" << Name << "\"\n"
399 OS << " const unsigned " << FUs[j]->getName()
402 OS << "}\n";
406 OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name
409 OS << " const unsigned NoBypass = 0;\n";
411 OS << " const unsigned " << BPs[j]->getName()
414 OS << "}\n";
543 OS << StageTable;
544 OS << OperandCycleTable;
545 OS << BypassTable;
555 EmitItineraries(raw_ostream &OS,
578 OS << "\n";
579 OS << "static const llvm::InstrItinerary ";
581 OS << '*' << Name << " = 0;\n";
586 OS << Name << "[] = {\n";
594 OS << " { " <<
603 OS << " { 0, ~0U, ~0U, ~0U, ~0U } // end marker\n";
604 OS << "};\n";
611 void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R,
613 OS << " ";
616 OS << V << Separator << " // " << Name;
618 OS << "MCSchedModel::Default" << Name << Separator;
619 OS << '\n';
623 raw_ostream &OS) {
626 OS << "\n// {Name, NumUnits, SuperIdx, IsBuffered}\n";
627 OS << "static const llvm::MCProcResourceDesc "
645 OS << " {DBGFIELD(\"" << PRDef->getName() << "\") ";
647 OS.indent(15 - PRDef->getName().size());
648 OS << PRDef->getValueAsInt("NumUnits") << ", " << SuperIdx << ", "
651 OS << ", Super=" << SuperDef->getName();
652 OS << "\n";
654 OS << "};\n";
999 raw_ostream &OS) {
1001 OS << "\n// {ProcResourceIdx, Cycles}\n"
1008 OS << " {" << format("%2d", WPREntry.ProcResourceIdx) << ", "
1011 OS << ',';
1012 OS << " // #" << WPRIdx << '\n';
1014 OS << "}; // " << Target << "WriteProcResTable\n";
1017 OS << "\n// {Cycles, WriteResourceID}\n"
1024 OS << " {" << format("%2d", WLEntry.Cycles) << ", "
1027 OS << ',';
1028 OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n';
1030 OS << "}; // " << Target << "WriteLatencyTable\n";
1033 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
1040 OS << " {" << RAEntry.UseIdx << ", "
1044 OS << ',';
1045 OS << " // #" << RAIdx << '\n';
1047 OS << "}; // " << Target << "ReadAdvanceTable\n";
1058 OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup,"
1060 OS << "static const llvm::MCSchedClassDesc "
1067 OS << " {DBGFIELD(\"InvalidSchedClass\") "
1074 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") ";
1076 OS.indent(18 - SchedClass.Name.size());
1077 OS << MCDesc.NumMicroOps
1086 OS << ',';
1087 OS << " // #" << SCIdx << '\n';
1089 OS << "}; // " << PI->ModelName << "SchedClasses\n";
1093 void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
1099 EmitProcessorResources(*PI, OS);
1105 OS << "\n";
1106 OS << "static const llvm::MCSchedModel " << PI->ModelName << "(\n";
1107 EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ',');
1108 EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ',');
1109 EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ',');
1110 EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ',');
1111 EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ',');
1112 OS << " " << PI->Index << ", // Processor ID\n";
1114 OS << " " << PI->ModelName << "ProcResources" << ",\n"
1120 OS << " 0, 0, 0, 0, // No instruction-level machine model.\n";
1122 OS << " " << PI->ItinsDef->getName() << ");\n";
1124 OS << " 0); // No Itinerary\n";
1131 void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
1138 OS << "\n";
1139 OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
1153 OS << " { \"" << Name << "\", (const void *)&" << ProcModelName << " }";
1156 if (++i < N) OS << ",";
1158 OS << "\n";
1162 OS << "};\n";
1168 void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
1169 OS << "#ifdef DBGFIELD\n"
1181 EmitStageAndOperandCycleData(OS, ProcItinLists);
1182 EmitItineraries(OS, ProcItinLists);
1184 OS << "\n// ===============================================================\n"
1192 EmitSchedClassTables(SchedTables, OS);
1195 EmitProcessorModels(OS);
1197 EmitProcessorLookup(OS);
1199 OS << "#undef DBGFIELD";
1203 raw_ostream &OS) {
1204 OS << "unsigned " << ClassName
1212 OS << (*PI)->getValueAsString("Code") << '\n';
1222 OS << " switch (SchedClass) {\n";
1226 OS << " case " << *VCI << ": // " << SC.Name << '\n';
1239 OS << " ";
1241 OS << "if (SchedModel->getProcessorID() == " << *PI << ") ";
1242 OS << "{ // " << (SchedModels.procModelBegin() + *PI)->ModelName
1247 OS << " if (";
1255 OS << "\n && ";
1256 OS << "(" << (*RI)->getValueAsString("Predicate") << ")";
1258 OS << ")\n"
1262 OS << " }\n";
1272 OS << " return " << SCIdx << ";\n";
1273 OS << " break;\n";
1275 OS << " };\n";
1277 OS << " report_fatal_error(\"Expected a variant SchedClass\");\n"
1285 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
1292 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
1295 OS << Target;
1296 OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n"
1301 OS << "}\n";
1305 OS << " InitMCProcessorInfo(CPU, FS);\n"
1316 OS << " if ((Bits & " << Target << "::"
1320 OS << " if ((Bits & " << Target << "::"
1326 OS << "}\n";
1332 void SubtargetEmitter::run(raw_ostream &OS) {
1333 emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
1335 OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
1336 OS << "#undef GET_SUBTARGETINFO_ENUM\n";
1338 OS << "namespace llvm {\n";
1339 Enumeration(OS, "SubtargetFeature", true);
1340 OS << "} // End llvm namespace \n";
1341 OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
1343 OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
1344 OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
1346 OS << "namespace llvm {\n";
1348 OS << "namespace {\n";
1350 unsigned NumFeatures = FeatureKeyValues(OS);
1351 OS << "\n";
1352 unsigned NumProcs = CPUKeyValues(OS);
1353 OS << "\n";
1354 EmitSchedModel(OS);
1355 OS << "\n";
1357 OS << "}\n";
1361 OS << "static inline void Init" << Target
1364 OS << " II->InitMCSubtargetInfo(TT, CPU, FS, ";
1366 OS << Target << "FeatureKV, ";
1368 OS << "0, ";
1370 OS << Target << "SubTypeKV, ";
1372 OS << "0, ";
1373 OS << '\n'; OS.indent(22);
1374 OS << Target << "ProcSchedKV, "
1379 OS << '\n'; OS.indent(22);
1380 OS << Target << "Stages, "
1384 OS << "0, 0, 0, ";
1385 OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
1387 OS << "} // End llvm namespace \n";
1389 OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";
1391 OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
1392 OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n";
1394 OS << "#include \"llvm/Support/Debug.h\"\n";
1395 OS << "#include \"llvm/Support/raw_ostream.h\"\n";
1396 ParseFeaturesFunction(OS, NumFeatures, NumProcs);
1398 OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
1401 OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
1402 OS << "#undef GET_SUBTARGETINFO_HEADER\n";
1405 OS << "namespace llvm {\n";
1406 OS << "class DFAPacketizer;\n";
1407 OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
1416 OS << "} // End llvm namespace \n";
1418 OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
1420 OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
1421 OS << "#undef GET_SUBTARGETINFO_CTOR\n";
1423 OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n";
1424 OS << "namespace llvm {\n";
1425 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
1426 OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n";
1427 OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
1428 OS << "extern const llvm::MCWriteProcResEntry "
1430 OS << "extern const llvm::MCWriteLatencyEntry "
1432 OS << "extern const llvm::MCReadAdvanceEntry "
1436 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
1437 OS << "extern const unsigned " << Target << "OperandCycles[];\n";
1438 OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
1441 OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, "
1446 OS << Target << "FeatureKV, ";
1448 OS << "0, ";
1450 OS << Target << "SubTypeKV, ";
1452 OS << "0, ";
1453 OS << '\n'; OS.indent(22);
1454 OS << Target << "ProcSchedKV, "
1458 OS << '\n'; OS.indent(22);
1460 OS << Target << "Stages, "
1464 OS << "0, 0, 0, ";
1465 OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
1467 EmitSchedModelHelpers(ClassName, OS);
1469 OS << "} // End llvm namespace \n";
1471 OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
1476 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
1478 SubtargetEmitter(RK, CGTarget).run(OS);