Lines Matching refs:MIB
1776 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1782 MIB.addReg(0).addImm(1 << ShAmt)
1788 addRegOffset(MIB, leaInReg, true, 1);
1792 addRegOffset(MIB, leaInReg, true, -1);
1798 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1809 addRegReg(MIB, leaInReg, true, leaInReg, false);
1814 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
1816 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1819 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1827 MachineInstr *NewMI = MIB;
2978 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2980 MIB.addOperand(Addr[i]);
2981 MIB.addReg(SrcReg, getKillRegState(isKill));
2982 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2983 NewMIs.push_back(MIB);
3012 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3014 MIB.addOperand(Addr[i]);
3015 (*MIB).setMemRefs(MMOBegin, MMOEnd);
3016 NewMIs.push_back(MIB);
3538 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
3539 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
3540 return &*MIB;
3550 MachineInstrBuilder MIB(NewMI);
3553 MIB.addOperand(MOs[i]);
3555 addOffset(MIB, 0);
3561 MIB.addOperand(MO);
3565 MIB.addOperand(MO);
3567 return MIB;
3576 MachineInstrBuilder MIB(NewMI);
3584 MIB.addOperand(MOs[i]);
3586 addOffset(MIB, 0);
3588 MIB.addOperand(MO);
3591 return MIB;
3598 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
3602 MIB.addOperand(MOs[i]);
3604 addOffset(MIB, 0);
3605 return MIB.addImm(0);
4114 MachineInstrBuilder MIB(DataMI);
4117 MIB.addReg(Reg, RegState::Define);
4119 MIB.addOperand(BeforeOps[i]);
4121 MIB.addReg(Reg);
4123 MIB.addOperand(AfterOps[i]);
4126 MIB.addReg(MO.getReg(),