Lines Matching refs:NewOp
6169 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6170 if (NewOp.getNode())
6171 return NewOp;
6588 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6589 if (NewOp.getNode())
6590 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6596 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6597 if (NewOp.getNode()) {
6598 EVT NewVT = NewOp.getValueType();
6599 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6601 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6605 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6606 if (NewOp.getNode()) {
6607 EVT NewVT = NewOp.getValueType();
6608 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6609 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6659 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6660 if (NewOp.getNode())
6661 return NewOp;
6902 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
6903 if (NewOp.getNode())
6904 return NewOp;
6908 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6909 if (NewOp.getNode())
6910 return NewOp;
6914 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
6915 if (NewOp.getNode())
6916 return NewOp;
11475 SelectionDAG &DAG, unsigned NewOp) {
11489 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
13940 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13941 if (NewOp.getNode())
13942 return NewOp;
15766 unsigned NewOp = 0;
15769 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
15770 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
15773 return DAG.getNode(NewOp, N->getDebugLoc(), N->getValueType(0),