Lines Matching defs:DCI
13604 TargetLowering::DAGCombinerInfo &DCI,
13661 return DCI.CombineTo(N, InsV);
13672 return DCI.CombineTo(N, InsV);
13679 return DCI.CombineTo(N, InsV);
13687 TargetLowering::DAGCombinerInfo &DCI,
13694 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
13700 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13721 TargetLowering::DAGCombinerInfo &DCI,
13723 if (!DCI.isBeforeLegalizeOps())
13845 TargetLowering::DAGCombinerInfo &DCI) {
13846 if (DCI.isBeforeLegalizeOps())
13939 TargetLowering::DAGCombinerInfo &DCI) {
13940 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
14026 TargetLowering::DAGCombinerInfo &DCI,
14308 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
14309 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
14320 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
14321 DCI.isBeforeLegalizeOps());
14324 DCI.CommitTargetLoweringOpt(TLO);
14428 TargetLowering::DAGCombinerInfo &DCI,
14491 return DCI.CombineTo(N, Cond, SDValue());
14508 return DCI.CombineTo(N, Cond, SDValue());
14551 return DCI.CombineTo(N, Cond, SDValue());
14572 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
14573 // the DCI.xxxx conditions are provided to postpone the optimization as
14605 TargetLowering::DAGCombinerInfo &DCI) {
14606 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
14659 DCI.CombineTo(N, NewMul, false);
14711 TargetLowering::DAGCombinerInfo &DCI,
14779 !DCI.isBeforeLegalize())
14838 TargetLowering::DAGCombinerInfo &DCI,
14943 TargetLowering::DAGCombinerInfo &DCI,
14945 if (DCI.isBeforeLegalizeOps())
14948 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
15019 TargetLowering::DAGCombinerInfo &DCI,
15021 if (DCI.isBeforeLegalizeOps())
15024 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
15202 TargetLowering::DAGCombinerInfo &DCI,
15204 if (DCI.isBeforeLegalizeOps())
15242 TargetLowering::DAGCombinerInfo &DCI,
15352 return DCI.CombineTo(N, Shuff, TF, true);
15793 TargetLowering::DAGCombinerInfo &DCI) {
15800 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
15801 !DCI.isBeforeLegalizeOps());
15805 DCI.CommitTargetLoweringOpt(TLO);
15824 TargetLowering::DAGCombinerInfo &DCI,
15826 if (!DCI.isBeforeLegalizeOps())
15919 TargetLowering::DAGCombinerInfo &DCI,
15957 if (!DCI.isBeforeLegalizeOps())
16013 TargetLowering::DAGCombinerInfo &DCI,
16042 TargetLowering::DAGCombinerInfo &DCI,
16126 X86TargetLowering::DAGCombinerInfo &DCI) {
16143 return DCI.CombineTo(N, Res1, CarryOut);
16239 DAGCombinerInfo &DCI) const {
16240 SelectionDAG &DAG = DCI.DAG;
16244 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
16246 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
16247 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
16250 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
16251 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
16254 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
16255 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
16256 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
16257 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
16258 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
16270 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
16273 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
16274 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
16275 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
16277 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
16278 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
16292 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);