Lines Matching defs:Z*
405 setBooleanContents(ZeroOrOneBooleanContent);
406 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
1201 SDValue Zero = DAG.getConstant(0, PtrVT);
1204 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1205 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1339 SDValue Zext = Op.getOperand(0);
1342 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1345 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1385 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1408 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3327 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4019 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
4205 SDValue Z = DAG.getConstant(0, MVT::i32);
4206 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
4207 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
4679 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4696 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4704 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4707 LHS, RHS, Zero, DAG, dl);
4949 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
5013 if (ptrA != ZeroReg) {
5043 .addReg(ZeroReg).addReg(PtrReg);
5054 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
5338 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
5371 if (ptrA != ZeroReg) {
5408 .addReg(ZeroReg).addReg(PtrReg);
5424 .addReg(ZeroReg).addReg(PtrReg);
5433 .addReg(ZeroReg).addReg(PtrReg);