Lines Matching refs:sub
1679 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1687 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1700 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1723 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1731 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1742 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1751 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1773 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1866 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1948 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2868 // Allow Q regs and just interpret them as the two D sub-registers.
2898 // Allow Q regs and just interpret them as the two D sub-registers.
2926 // Allow Q regs and just interpret them as the two D sub-registers.
3106 // them as the two D sub-registers.
3134 // Allow Q regs and just interpret them as the two D sub-registers.
3180 // them as the two D sub-registers.
4771 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4840 (isThumbTwo() && Mnemonic == "sub")) &&
4849 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4854 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4921 // Register-register 'add/sub' for thumb does not have a cc_out operand
4923 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4926 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
7020 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7022 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||