Lines Matching refs:LHS
2776 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2830 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2835 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2839 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2841 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2920 SDValue LHS = Op.getOperand(0);
2927 if (LHS.getValueType() == MVT::i32) {
2930 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2938 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2945 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3025 SDValue LHS = Op.getOperand(2);
3031 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3045 if (LHS.getValueType() == MVT::f32) {
3046 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3047 bitcastf32Toi32(LHS, DAG), Mask);
3050 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3058 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3075 SDValue LHS = Op.getOperand(2);
3080 if (LHS.getValueType() == MVT::i32) {
3082 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3088 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3102 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
4512 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4538 if (LHSID == (1*9+2)*9+3) return LHS;
4544 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4545 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
8866 SDValue LHS = N->getOperand(2);
8872 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
8874 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
8889 // If LHS is NaN, an ordered comparison will be false and the result will
8890 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
8893 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
8900 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8911 // If LHS is NaN, an ordered comparison will be false and the result will
8912 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
8915 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
8922 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8930 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
8943 SDValue LHS = Cmp.getOperand(0);
8969 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
8970 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
8974 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
8975 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
9521 // Bits are known zero/one if known on the LHS and RHS.