Lines Matching refs:OpIdx
101 unsigned OpIdx);
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
241 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
243 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
271 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
273 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
275 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
277 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
355 unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const;
356 unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) const;
357 unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) const;
358 unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) const;
359 unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) const;
360 unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) const;
925 unsigned OpIdx) {
928 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
929 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
1018 unsigned OpIdx = 0;
1020 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1027 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1035 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1052 Binary |= getMachineOpValue(MI, OpIdx++);
1054 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1055 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1065 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1066 ++OpIdx;
1075 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1076 ++OpIdx;
1081 const MachineOperand &MO = MI.getOperand(OpIdx);
1084 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx));
1120 unsigned OpIdx = 0;
1126 ++OpIdx;
1135 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1142 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1145 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1146 ++OpIdx;
1148 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1150 ? 0 : MI.getOperand(OpIdx+1).getImm();
1191 unsigned OpIdx = 0;
1197 ++OpIdx;
1202 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1206 ++OpIdx;
1213 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1216 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1217 ++OpIdx;
1219 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1221 ? 0 : MI.getOperand(OpIdx+1).getImm();
1276 unsigned OpIdx = 0;
1278 ++OpIdx;
1281 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1292 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1319 unsigned OpIdx = 0;
1321 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1324 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1327 Binary |= getMachineOpValue(MI, OpIdx++);
1330 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1334 if (MCID.getNumOperands() > OpIdx &&
1335 !MCID.OpInfo[OpIdx].isPredicate() &&
1336 !MCID.OpInfo[OpIdx].isOptionalDef())
1337 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1351 unsigned OpIdx = 0;
1354 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1356 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1357 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1365 ++OpIdx;
1371 if (MI.getOperand(OpIdx).isImm() &&
1372 !MCID.OpInfo[OpIdx].isPredicate() &&
1373 !MCID.OpInfo[OpIdx].isOptionalDef())
1374 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1394 unsigned OpIdx = 0;
1397 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1399 const MachineOperand &MO = MI.getOperand(OpIdx++);
1400 if (OpIdx == MCID.getNumOperands() ||
1401 MCID.OpInfo[OpIdx].isPredicate() ||
1402 MCID.OpInfo[OpIdx].isOptionalDef()) {
1413 Binary |= getMachineOpValue(MI, OpIdx++);
1416 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1548 unsigned OpIdx) const {
1549 unsigned RegD = MI.getOperand(OpIdx).getReg();
1563 unsigned OpIdx) const {
1564 unsigned RegN = MI.getOperand(OpIdx).getReg();
1578 unsigned OpIdx) const {
1579 unsigned RegM = MI.getOperand(OpIdx).getReg();
1601 unsigned OpIdx = 0;
1607 Binary |= encodeVFPRd(MI, OpIdx++);
1610 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1611 ++OpIdx;
1615 Binary |= encodeVFPRn(MI, OpIdx++);
1617 if (OpIdx == MCID.getNumOperands() ||
1618 MCID.OpInfo[OpIdx].isPredicate() ||
1619 MCID.OpInfo[OpIdx].isOptionalDef()) {
1626 Binary |= encodeVFPRm(MI, OpIdx);
1694 unsigned OpIdx = 0;
1697 Binary |= encodeVFPRd(MI, OpIdx++);
1700 const MachineOperand &Base = MI.getOperand(OpIdx++);
1705 const MachineOperand &Offset = MI.getOperand(OpIdx);
1733 unsigned OpIdx = 0;
1735 ++OpIdx;
1738 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1749 Binary |= encodeVFPRd(MI, OpIdx+2);
1753 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1770 unsigned OpIdx) const {
1771 unsigned RegD = MI.getOperand(OpIdx).getReg();
1780 unsigned OpIdx) const {
1781 unsigned RegN = MI.getOperand(OpIdx).getReg();
1790 unsigned OpIdx) const {
1791 unsigned RegM = MI.getOperand(OpIdx).getReg();
1883 unsigned OpIdx = 0;
1884 Binary |= encodeNEONRd(MI, OpIdx++);
1885 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1886 ++OpIdx;
1887 Binary |= encodeNEONRm(MI, OpIdx);
1898 unsigned OpIdx = 0;
1899 Binary |= encodeNEONRd(MI, OpIdx++);
1900 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1901 ++OpIdx;
1902 Binary |= encodeNEONRn(MI, OpIdx++);
1903 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1904 ++OpIdx;
1905 Binary |= encodeNEONRm(MI, OpIdx);