Lines Matching refs:VT
89 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
93 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
181 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
184 unsigned NumMaskElts = VT.getVectorNumElements();
255 EVT VT = CFP->getValueType(0);
258 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
260 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
263 EVT OrigVT = VT;
264 EVT SVT = VT;
274 VT = SVT;
286 VT, false, false, Alignment);
305 EVT VT = Val.getValueType();
310 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
388 // Get the half-size VT
397 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
426 EVT VT = LD->getValueType(0);
429 if (VT.isFloatingPoint() || VT.isVector()) {
439 if (LoadedVT != VT)
440 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
441 ISD::ANY_EXTEND, dl, VT, Result);
501 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
512 // Compute the new VT that is half the size of the old one. This is an
530 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
535 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
540 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
545 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
554 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
555 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
581 EVT VT = Tmp1.getValueType();
582 EVT EltVT = VT.getVectorElementType();
585 SDValue StackPtr = DAG.CreateStackTemporary(VT);
605 return DAG.getLoad(VT, dl, Ch, StackPtr,
713 EVT VT = Value.getValueType();
714 switch (TLI.getOperationAction(ISD::STORE, VT)) {
734 assert(VT.isVector() && "Unknown legal promote case!");
736 TLI.getTypeToPromoteTo(ISD::STORE, VT), Value);
865 EVT VT = Node->getValueType(0);
869 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
893 assert(VT.isVector() && "Cannot promote this load!");
895 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
900 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
1446 EVT VT = Node->getValueType(0);
1447 EVT EltVT = VT.getVectorElementType();
1449 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1488 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1559 EVT VT = Node->getValueType(0);
1570 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1575 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1576 DAG.getConstant(-(uint64_t)Align, VT));
1577 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1590 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1651 LHS = DAG.getSetCC(dl, VT, RHS, LHS, InvCC);
1661 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1662 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1665 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1666 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1668 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1749 EVT VT = Node->getValueType(0);
1751 EVT EltVT = VT.getVectorElementType();
1778 return DAG.getUNDEF(VT);
1781 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1811 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1826 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1829 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1831 Vec2 = DAG.getUNDEF(VT);
1834 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2378 EVT VT = Op.getValueType();
2379 EVT SHVT = TLI.getShiftAmountTy(VT);
2381 switch (VT.getSimpleVT().SimpleTy) {
2384 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2385 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2386 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2388 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2389 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2390 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2391 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2392 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2393 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2394 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2395 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2396 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2398 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2399 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2400 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2401 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2402 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2403 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2404 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2405 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2406 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2407 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2408 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2409 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2410 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2411 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2412 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2413 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2414 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2415 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2416 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2417 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2418 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2441 EVT VT = Op.getValueType();
2442 EVT ShVT = TLI.getShiftAmountTy(VT);
2443 unsigned Len = VT.getSizeInBits();
2445 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2451 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2452 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2453 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2454 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2457 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2458 DAG.getNode(ISD::AND, dl, VT,
2459 DAG.getNode(ISD::SRL, dl, VT, Op,
2463 Op = DAG.getNode(ISD::ADD, dl, VT,
2464 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2465 DAG.getNode(ISD::AND, dl, VT,
2466 DAG.getNode(ISD::SRL, dl, VT, Op,
2470 Op = DAG.getNode(ISD::AND, dl, VT,
2471 DAG.getNode(ISD::ADD, dl, VT, Op,
2472 DAG.getNode(ISD::SRL, dl, VT, Op,
2476 Op = DAG.getNode(ISD::SRL, dl, VT,
2477 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2495 EVT VT = Op.getValueType();
2496 EVT ShVT = TLI.getShiftAmountTy(VT);
2497 unsigned len = VT.getSizeInBits();
2500 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2501 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2503 Op = DAG.getNOT(dl, Op, VT);
2504 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2514 EVT VT = Op.getValueType();
2515 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2516 DAG.getNOT(dl, Op, VT),
2517 DAG.getNode(ISD::SUB, dl, VT, Op,
2518 DAG.getConstant(1, VT)));
2520 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2521 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2522 return DAG.getNode(ISD::SUB, dl, VT,
2523 DAG.getConstant(VT.getSizeInBits(), VT),
2524 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2525 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2532 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2539 switch (VT.SimpleTy) {
2548 switch (VT.SimpleTy) {
2557 switch (VT.SimpleTy) {
2566 switch (VT.SimpleTy) {
2575 switch (VT.SimpleTy) {
2584 switch (VT.SimpleTy) {
2593 switch (VT.SimpleTy) {
2602 switch (VT.SimpleTy) {
2727 EVT VT = Node->getValueType(0);
2728 if (VT.isInteger())
2729 Results.push_back(DAG.getConstant(0, VT));
2731 assert(VT.isFloatingPoint() && "Unknown value type!");
2732 Results.push_back(DAG.getConstantFP(0, VT));
2768 EVT VT = Node->getValueType(0);
2769 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2770 if (VT.isVector())
2771 ShiftAmountTy = VT;
2772 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2802 EVT VT = Node->getOperand(0).getValueType();
2804 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
2807 Tmp1 = DAG.getConstantFP(apf, VT);
2808 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2813 DAG.getNode(ISD::FSUB, dl, VT,
2823 EVT VT = Node->getValueType(0);
2848 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2854 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2903 EVT VT = Node->getValueType(0);
2904 EVT EltVT = VT.getVectorElementType();
2919 // Calculate new VT, the size of the new VT should be equal to original.
2921 VT.getSizeInBits()/NewEltVT.getSizeInBits());
2922 assert(NewVT.bitsEq(VT));
2924 // cast operands to new VT
2929 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
2934 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2945 VT = NewVT;
2949 unsigned NumElems = VT.getVectorNumElements();
2967 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3023 EVT VT = Node->getValueType(0);
3025 Tmp2 = DAG.getConstantFP(0.0, VT);
3028 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3029 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3138 EVT VT = Node->getValueType(0);
3139 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3140 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3142 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3143 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3148 EVT VT = Node->getValueType(0);
3149 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3150 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3152 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3153 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3154 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3155 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3160 EVT VT = Node->getValueType(0);
3161 SDVTList VTs = DAG.getVTList(VT, VT);
3167 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3173 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3175 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3176 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3177 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3195 EVT VT = Node->getValueType(0);
3196 SDVTList VTs = DAG.getVTList(VT, VT);
3197 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3219 EVT VT = Node->getValueType(0);
3220 SDVTList VTs = DAG.getVTList(VT, VT);
3221 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3234 EVT VT = Node->getValueType(0);
3235 SDVTList VTs = DAG.getVTList(VT, VT);
3241 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3242 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3243 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3244 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3316 EVT VT = Node->getValueType(0);
3317 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3326 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3327 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3328 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3329 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3330 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3334 VT.getSizeInBits() * 2))) {
3338 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3340 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3360 unsigned LoSize = VT.getSizeInBits();
3361 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3363 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3372 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3374 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3383 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3385 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3386 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3389 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3390 DAG.getConstant(0, VT), ISD::SETNE);
3488 EVT VT = Node->getValueType(0);
3489 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3490 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3536 EVT VT = Node->getValueType(0);
3537 assert(VT.isVector() && "Unable to legalize non-vector shift");
3538 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3539 unsigned NumElem = VT.getVectorNumElements();
3544 VT.getScalarType(),
3547 VT.getScalarType(),
3550 VT.getScalarType(), Ex, Sh));
3607 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))