Lines Matching refs:AR
159 const SCEVAddRecExpr *AR = cast<SCEVAddRecExpr>(this);
160 OS << "{" << *AR->getOperand(0);
161 for (unsigned i = 1, e = AR->getNumOperands(); i != e; ++i)
162 OS << ",+," << *AR->getOperand(i);
164 if (AR->getNoWrapFlags(FlagNUW))
166 if (AR->getNoWrapFlags(FlagNSW))
168 if (AR->getNoWrapFlags(FlagNW) &&
169 !AR->getNoWrapFlags((NoWrapFlags)(FlagNUW | FlagNSW)))
171 WriteAsOperand(OS, AR->getLoop()->getHeader(), /*PrintType=*/false);
935 if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(Op))
936 if (AR->isAffine()) {
937 const SCEV *Start = AR->getStart();
938 const SCEV *Step = AR->getStepRecurrence(*this);
939 unsigned BitWidth = getTypeSizeInBits(AR->getType());
940 const Loop *L = AR->getLoop();
944 if (AR->getNoWrapFlags(SCEV::FlagNUW))
947 L, AR->getNoWrapFlags());
959 // Manually compute the final value for AR, checking for
981 // Cache knowledge of AR NUW, which is propagated to this AddRec.
982 const_cast<SCEVAddRecExpr *>(AR)->setNoWrapFlags(SCEV::FlagNUW);
986 L, AR->getNoWrapFlags());
995 // Cache knowledge of AR NW, which is propagated to this AddRec.
997 const_cast<SCEVAddRecExpr *>(AR)->setNoWrapFlags(SCEV::FlagNW);
1001 L, AR->getNoWrapFlags());
1012 if (isLoopBackedgeGuardedByCond(L, ICmpInst::ICMP_ULT, AR, N) ||
1015 AR->getPostIncExpr(*this), N))) {
1016 // Cache knowledge of AR NUW, which is propagated to this AddRec.
1017 const_cast<SCEVAddRecExpr *>(AR)->setNoWrapFlags(SCEV::FlagNUW);
1021 L, AR->getNoWrapFlags());
1026 if (isLoopBackedgeGuardedByCond(L, ICmpInst::ICMP_UGT, AR, N) ||
1029 AR->getPostIncExpr(*this), N))) {
1030 // Cache knowledge of AR NW, which is propagated to this AddRec.
1032 const_cast<SCEVAddRecExpr *>(AR)->setNoWrapFlags(SCEV::FlagNW);
1036 L, AR->getNoWrapFlags());
1071 // The recurrence AR has been shown to have no signed wrap. Typically, if we can
1072 // prove NSW for AR, then we can just as easily prove NSW for its preincrement
1077 static const SCEV *getPreStartForSignExtend(const SCEVAddRecExpr *AR,
1080 const Loop *L = AR->getLoop();
1081 const SCEV *Start = AR->getStart();
1082 const SCEV *Step = AR->getStepRecurrence(*SE);
1101 // This is a postinc AR. Check for overflow on the preinc recurrence using the
1113 unsigned BitWidth = SE->getTypeSizeInBits(AR->getType());
1139 static const SCEV *getSignExtendAddRecStart(const SCEVAddRecExpr *AR,
1142 const SCEV *PreStart = getPreStartForSignExtend(AR, Ty, SE);
1144 return SE->getSignExtendExpr(AR->getStart(), Ty);
1146 return SE->getAddExpr(SE->getSignExtendExpr(AR->getStepRecurrence(*SE), Ty),
1201 if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(Op))
1202 if (AR->isAffine()) {
1203 const SCEV *Start = AR->getStart();
1204 const SCEV *Step = AR->getStepRecurrence(*this);
1205 unsigned BitWidth = getTypeSizeInBits(AR->getType());
1206 const Loop *L = AR->getLoop();
1210 if (AR->getNoWrapFlags(SCEV::FlagNSW))
1211 return getAddRecExpr(getSignExtendAddRecStart(AR, Ty, this),
1225 // Manually compute the final value for AR, checking for
1247 // Cache knowledge of AR NSW, which is propagated to this AddRec.
1248 const_cast<SCEVAddRecExpr *>(AR)->setNoWrapFlags(SCEV::FlagNSW);
1250 return getAddRecExpr(getSignExtendAddRecStart(AR, Ty, this),
1252 L, AR->getNoWrapFlags());
1261 // Cache knowledge of AR NSW, which is propagated to this AddRec.
1262 const_cast<SCEVAddRecExpr *>(AR)->setNoWrapFlags(SCEV::FlagNSW);
1264 return getAddRecExpr(getSignExtendAddRecStart(AR, Ty, this),
1266 L, AR->getNoWrapFlags());
1277 (isLoopBackedgeGuardedByCond(L, Pred, AR, OverflowLimit) ||
1279 isLoopBackedgeGuardedByCond(L, Pred, AR->getPostIncExpr(*this),
1281 // Cache knowledge of AR NSW, then propagate NSW to the wide AddRec.
1282 const_cast<SCEVAddRecExpr *>(AR)->setNoWrapFlags(SCEV::FlagNSW);
1283 return getAddRecExpr(getSignExtendAddRecStart(AR, Ty, this),
1285 L, AR->getNoWrapFlags());
1334 if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(Op)) {
1336 for (SCEVAddRecExpr::op_iterator I = AR->op_begin(), E = AR->op_end();
1339 return getAddRecExpr(Ops, AR->getLoop(), SCEV::FlagNW);
2142 if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(LHS))
2144 dyn_cast<SCEVConstant>(AR->getStepRecurrence(*this))) {
2149 getZeroExtendExpr(AR, ExtTy) ==
2150 getAddRecExpr(getZeroExtendExpr(AR->getStart(), ExtTy),
2152 AR->getLoop(), SCEV::FlagAnyWrap)) {
2154 for (unsigned i = 0, e = AR->getNumOperands(); i != e; ++i)
2155 Operands.push_back(getUDivExpr(AR->getOperand(i), RHS));
2156 return getAddRecExpr(Operands, AR->getLoop(),
2162 const SCEVConstant *StartC = dyn_cast<SCEVConstant>(AR->getStart());
2164 getZeroExtendExpr(AR, ExtTy) ==
2165 getAddRecExpr(getZeroExtendExpr(AR->getStart(), ExtTy),
2167 AR->getLoop(), SCEV::FlagAnyWrap)) {
2172 AR->getLoop(), SCEV::FlagNW);
5632 if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(RHS)) {
5633 const Loop *L = AR->getLoop();
5907 if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(LHS))
5909 AR->getLoop(), Pred, AR->getStart(), RHS) &&
5911 AR->getLoop(), Pred, AR->getPostIncExpr(*this), RHS))
5913 if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(RHS))
5915 AR->getLoop(), Pred, LHS, AR->getStart()) &&
5917 AR->getLoop(), Pred, LHS, AR->getPostIncExpr(*this)))
6744 const SCEVAddRecExpr *AR = cast<SCEVAddRecExpr>(S);
6747 if (AR->getLoop() == L)
6754 // This recurrence is variant w.r.t. L if L contains AR's loop.
6755 if (L->contains(AR->getLoop()))
6758 // This recurrence is invariant w.r.t. L if AR's loop contains L.
6759 if (AR->getLoop()->contains(L))
6764 for (SCEVAddRecExpr::op_iterator I = AR->op_begin(), E = AR->op_end();
6847 const SCEVAddRecExpr *AR = cast<SCEVAddRecExpr>(S);
6848 if (!DT->dominates(AR->getLoop()->getHeader(), BB))