Lines Matching +defs:event +defs:seq
1039 Standard: \"clk'event and clk = '1'\"
1066 elsif <clock>'event and <clock> = '1' then -- rising clock edge
2594 (define-key vhdl-template-map "ps" 'vhdl-template-process-seq)
3278 ["Process (Seq)" vhdl-template-process-seq t]
4856 "endprimitive" "endspecify" "endtable" "endtask" "event"
4904 "event" "active" "last_event" "last_active" "last_value"
7753 ;; 4. search for if/elsif conditions containing an event (sequential code)
7791 seq-region-list)
7852 (when (re-search-backward "\\('event\\|\\<\\(falling\\|rising\\)_edge\\)\\>" beg t)
7856 (setq seq-region-list (cons (cons end (point)) seq-region-list))
7865 (and seq-region-list
7866 (let ((tmp-list seq-region-list))
7874 (not (and (match-string 3) ; not event attribute
7876 '("event" "last_event" "transaction")))))
8060 (defun vhdl-character-to-event (arg))
8061 (defalias 'vhdl-character-to-event
8062 (if (fboundp 'character-to-event) 'character-to-event 'identity))
8127 (list (vhdl-character-to-event next-input))))))
8129 (list (vhdl-character-to-event next-input)))
9283 label seq input-signals clock reset final-pos)
9284 (setq seq (if kind (eq kind 'seq)
9297 (if (not seq)
9314 (when seq (setq reset (vhdl-template-seq-process clock reset)))
9331 (insert (if seq "sequential" "combinational") "\n")
9334 (if (not seq)
9351 (defun vhdl-template-process-seq ()
9354 (vhdl-template-process 'seq))
9740 (insert "'event")
9749 (defun vhdl-template-seq-process (clock reset)
9768 (insert clock "'event")
10061 (list (vhdl-character-to-event next-input)))))) ; pushback the char
10614 ;; delete CR which is still in event queue
10615 (if (fboundp 'enqueue-eval-event)
10616 (enqueue-eval-event 'delete-char -1)
10618 (list (vhdl-character-to-event ?\177))))))))