Lines Matching defs:pc
57 r15, pc = r15,
199 V(void*, pc)
593 return (reg == ARMRegisters::sp) || (reg == ARMRegisters::pc);
849 ASSERT(rd != ARMRegisters::pc);
850 ASSERT(rn != ARMRegisters::pc);
860 ASSERT(rd != ARMRegisters::pc);
861 ASSERT(rn != ARMRegisters::pc);
894 ASSERT(rd != ARMRegisters::pc);
895 ASSERT(rn != ARMRegisters::pc);
923 ASSERT(rd != ARMRegisters::pc);
924 ASSERT(rn != ARMRegisters::pc);
944 ASSERT(rd != ARMRegisters::pc);
945 ASSERT(rn != ARMRegisters::pc);
1011 ASSERT(rm != ARMRegisters::pc);
1037 ASSERT(rn != ARMRegisters::pc);
1045 ASSERT(rn != ARMRegisters::pc);
1056 ASSERT(rn != ARMRegisters::pc);
1118 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
1121 ASSERT(rn != ARMRegisters::pc); // LDR (literal)
1134 ASSERT(rn != ARMRegisters::pc);
1140 ASSERT(rn != ARMRegisters::pc); // LDR (literal)
1159 ASSERT(rt != ARMRegisters::pc);
1160 ASSERT(rn != ARMRegisters::pc);
1179 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
1182 ASSERT(rn != ARMRegisters::pc); // LDR (literal)
1192 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
1195 ASSERT(rn != ARMRegisters::pc); // LDR (literal)
1217 ASSERT(rt != ARMRegisters::pc);
1218 ASSERT(rn != ARMRegisters::pc);
1240 ASSERT(rn != ARMRegisters::pc); // LDRH (literal)
1252 ASSERT(rn != ARMRegisters::pc); // LDR (literal)
1263 ASSERT(rt != ARMRegisters::pc);
1264 ASSERT(rn != ARMRegisters::pc);
1286 ASSERT(rn != ARMRegisters::pc); // LDR (literal)
1298 ASSERT(rn != ARMRegisters::pc);
1310 ASSERT(rn != ARMRegisters::pc);
1515 ASSERT(!((1 << ARMRegisters::pc) & registerList) || !((1 << ARMRegisters::lr) & registerList));
1535 ASSERT(!((1 << ARMRegisters::pc) & registerList));
1562 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
1565 ASSERT(rt != ARMRegisters::pc);
1566 ASSERT(rn != ARMRegisters::pc);
1590 ASSERT(rt != ARMRegisters::pc);
1591 ASSERT(rn != ARMRegisters::pc);
1610 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
1613 ASSERT(rn != ARMRegisters::pc);
1623 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
1626 ASSERT(rt != ARMRegisters::pc);
1627 ASSERT(rn != ARMRegisters::pc);
1649 ASSERT(rt != ARMRegisters::pc);
1650 ASSERT(rn != ARMRegisters::pc);
1669 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
1672 ASSERT(rn != ARMRegisters::pc);
1682 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
1685 ASSERT(rt != ARMRegisters::pc);
1686 ASSERT(rn != ARMRegisters::pc);
1708 ASSERT(rt != ARMRegisters::pc);
1709 ASSERT(rn != ARMRegisters::pc);
1728 // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
1731 ASSERT(rn != ARMRegisters::pc);
1745 ASSERT(rd != ARMRegisters::pc);
1746 ASSERT(rn != ARMRegisters::pc);
1773 ASSERT(rd != ARMRegisters::pc);
1774 ASSERT(rn != ARMRegisters::pc);
1787 ASSERT(rd != ARMRegisters::pc);
1788 ASSERT(rn != ARMRegisters::pc);
1807 ASSERT(rd != ARMRegisters::pc);
1808 ASSERT(rn != ARMRegisters::pc);
1830 ASSERT(rd != ARMRegisters::pc);
1831 ASSERT(rn != ARMRegisters::pc);
1842 ASSERT(rd != ARMRegisters::pc);
1843 ASSERT(rn != ARMRegisters::pc);
1977 void vmrs(RegisterID reg = ARMRegisters::pc)