Lines Matching defs:pc
56 r15, pc = r15
116 V(void*, pc)
542 m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm, true);
547 m_buffer.putIntWithConstantInt(toARMWord(cc) | LoadUint32 | DataTransferUp | RN(ARMRegisters::pc) | RD(rd), imm);
718 ASSERT(reg <= ARMRegisters::pc);
725 ASSERT(reg <= ARMRegisters::pc);
732 ASSERT(reg <= ARMRegisters::pc);
739 ASSERT(reg <= ARMRegisters::pc);
740 ASSERT(shiftReg <= ARMRegisters::pc);
746 ASSERT(reg <= ARMRegisters::pc);
747 ASSERT(shiftReg <= ARMRegisters::pc);
753 ASSERT(reg <= ARMRegisters::pc);
754 ASSERT(shiftReg <= ARMRegisters::pc);
820 return loadBranchTarget(ARMRegisters::pc, cc, useConstantPool);
849 // Must be an ldr ..., [pc +/- imm]
860 // Must be an ldr ..., [pc +/- imm]
974 instruction[0] = LoadUint32 | AL | RN(ARMRegisters::pc) | RD(ARMRegisters::pc) | 4;
1132 ASSERT(reg <= ARMRegisters::pc);
1138 ASSERT(reg <= ARMRegisters::pc);
1144 ASSERT(reg <= ARMRegisters::pc);
1150 ASSERT(reg <= ARMRegisters::pc);