Lines Matching refs:getOpcode
1687 if (Arg.getOpcode() == ISD::CopyFromReg) {
1963 if (Copy->getOpcode() == ISD::CopyToReg) {
1969 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
1975 if (UI->getOpcode() != ISD::CopyToReg)
1992 } else if (Copy->getOpcode() == ISD::BITCAST) {
1997 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2007 if (UI->getOpcode() != ARMISD::RET_FLAG)
2763 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2849 unsigned Opc = Cmp.getOpcode();
2856 Opc = Cmp.getOpcode();
2877 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3168 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3180 switch (Op.getOpcode()) {
3210 switch (Op.getOpcode()) {
3234 switch (Op.getOpcode()) {
3255 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3256 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3433 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3435 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3470 assert(Op.getOpcode() == ISD::SHL_PARTS);
3533 if (N->getOpcode() == ISD::SHL)
3538 assert((N->getOpcode() == ISD::SRA ||
3539 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3548 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3565 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3584 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3671 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3674 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4197 if (V.getOpcode() == ISD::UNDEF)
4235 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4336 if (V.getOpcode() == ISD::UNDEF)
4338 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4441 if (Entry.getOpcode() == ISD::UNDEF) {
4601 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4634 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4640 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
4644 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
4785 if (Op0.getOpcode() != ISD::UNDEF)
4789 if (Op1.getOpcode() != ISD::UNDEF)
4803 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4806 BVN->getOpcode() != ISD::BUILD_VECTOR)
4827 if (N->getOpcode() != ISD::BUILD_VECTOR)
4853 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4863 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4873 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4882 if (N->getOpcode() == ISD::BITCAST) {
4884 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4891 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4909 unsigned Opcode = N->getOpcode();
4920 unsigned Opcode = N->getOpcode();
4997 return DAG.getNode(N0->getOpcode(), DL, VT,
5185 switch (Op.getOpcode()) {
5245 switch (Op.getOpcode()) {
5307 switch (N->getOpcode()) {
6632 switch (MI->getOpcode()) {
6652 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
6677 switch (MI->getOpcode()) {
6854 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
6985 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
6999 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7082 switch (N->getOpcode()) {
7115 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7164 SDValue FalseVal = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
7202 || N0.getOpcode() != ISD::BUILD_VECTOR
7203 || N1.getOpcode() != ISD::BUILD_VECTOR)
7218 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7228 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7229 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7283 if (V->getOpcode() == ISD::UMUL_LOHI ||
7284 V->getOpcode() == ISD::SMUL_LOHI)
7312 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
7326 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
7327 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
7328 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
7329 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
7338 if (AddeNode->getOpcode() != ISD::ADDE)
7364 unsigned Opc = MULOp->getOpcode();
7379 if (AddcOp0->getOpcode() == Opc) {
7383 if (AddcOp1->getOpcode() == Opc) {
7501 unsigned Opcode = N0.getOpcode();
7504 Opcode = N1.getOpcode();
7691 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
7696 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
7773 } else if (N1.getOpcode() == ISD::AND) {
7818 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
7862 if (N1.getOpcode() == ISD::AND) {
7885 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
7892 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
7928 if (Op0.getOpcode() == ISD::BITCAST)
7930 if (Op1.getOpcode() == ISD::BITCAST)
7932 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8035 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
8054 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8168 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
8169 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
8175 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
8176 Concat1Op1.getOpcode() != ISD::UNDEF)
8214 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
8215 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
8223 if (User->getOpcode() != ISD::ADD ||
8272 switch (N->getOpcode()) {
8351 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
8379 if (User->getOpcode() != ARMISD::VDUPLANE ||
8432 while (Op.getOpcode() == ISD::BITCAST)
8434 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
8493 Op.getOpcode() != ISD::FMUL)
8499 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
8501 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
8527 unsigned OpOpcode = Op.getNode()->getOpcode();
8537 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
8554 while (Op.getOpcode() == ISD::BITCAST)
8766 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
8772 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
8787 switch (N->getOpcode()) {
8799 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
8818 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
8831 switch (N->getOpcode()) {
8937 if (Cmp.getOpcode() != ARMISD::CMPZ)
8999 switch (N->getOpcode()) {
9342 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
9351 assert(Ptr->getOpcode() == ISD::ADD);
9357 isInc = (Ptr->getOpcode() == ISD::ADD);
9365 assert(Ptr->getOpcode() == ISD::ADD);
9373 if (Ptr->getOpcode() == ISD::ADD) {
9376 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
9387 isInc = (Ptr->getOpcode() == ISD::ADD);
9401 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
9408 assert(Ptr->getOpcode() == ISD::ADD);
9413 isInc = Ptr->getOpcode() == ISD::ADD;
9499 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
9518 switch (Op.getOpcode()) {