Lines Matching defs:?A
1196 CCValAssign VA = RVLocs[i];
1199 if (VA.needsCustom()) {
1201 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1205 VA = RVLocs[++i]; // skip ahead to next loc
1206 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1212 if (VA.getLocVT() == MVT::v2f64) {
1217 VA = RVLocs[++i]; // skip ahead to next loc
1218 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1221 VA = RVLocs[++i]; // skip ahead to next loc
1222 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1230 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1236 switch (VA.getLocInfo()) {
1240 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1255 const CCValAssign &VA,
1257 unsigned LocMemOffset = VA.getLocMemOffset();
1268 CCValAssign &VA, CCValAssign &NextVA,
1275 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1357 CCValAssign &VA = ArgLocs[i];
1363 switch (VA.getLocInfo()) {
1367 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1370 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1373 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1376 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1381 if (VA.needsCustom()) {
1382 if (VA.getLocVT() == MVT::v2f64) {
1389 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1391 VA = ArgLocs[++i]; // skip ahead to next loc
1392 if (VA.isRegLoc()) {
1394 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1396 assert(VA.isMemLoc());
1399 dl, DAG, VA, Flags));
1402 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1405 } else if (VA.isRegLoc()) {
1406 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1408 assert(VA.isMemLoc());
1430 unsigned LocMemOffset = VA.getLocMemOffset();
1446 assert(VA.isMemLoc());
1449 dl, DAG, VA, Flags));
1831 CCValAssign &VA = ArgLocs[i];
1832 EVT RegVT = VA.getLocVT();
1835 if (VA.getLocInfo() == CCValAssign::Indirect)
1837 if (VA.needsCustom()) {
1842 if (!VA.isRegLoc())
1852 } else if (!VA.isRegLoc()) {
1853 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1896 CCValAssign &VA = RVLocs[i];
1897 assert(VA.isRegLoc() && "Can only return in registers!");
1901 switch (VA.getLocInfo()) {
1905 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1909 if (VA.needsCustom()) {
1910 if (VA.getLocVT() == MVT::v2f64) {
1917 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1919 VA = RVLocs[++i]; // skip ahead to next loc
1920 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1923 VA = RVLocs[++i]; // skip ahead to next loc
1933 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1935 VA = RVLocs[++i]; // skip ahead to next loc
1936 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1939 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2061 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2065 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2070 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2086 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2088 DebugLoc dl = GA->getDebugLoc();
2095 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2127 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2130 const GlobalValue *GV = GA->getGlobal();
2131 DebugLoc dl = GA->getDebugLoc();
2145 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2183 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2185 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2190 return LowerToTLSGeneralDynamicModel(GA, DAG);
2193 return LowerToTLSExecModels(GA, DAG, model);
2477 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2490 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2624 CCValAssign &VA = ArgLocs[i];
2625 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
2626 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
2628 if (VA.isRegLoc()) {
2629 EVT RegVT = VA.getLocVT();
2631 if (VA.needsCustom()) {
2634 if (VA.getLocVT() == MVT::v2f64) {
2635 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2637 VA = ArgLocs[++i]; // skip ahead to next loc
2639 if (VA.isMemLoc()) {
2640 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2646 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2655 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2674 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2681 switch (VA.getLocInfo()) {
2685 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2689 DAG.getValueType(VA.getValVT()));
2690 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2694 DAG.getValueType(VA.getValVT()));
2695 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2701 } else { // VA.isRegLoc()
2704 assert(VA.isMemLoc());
2705 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2724 Ins[VA.getValNo()].PartOffset,
2725 VA.getLocMemOffset(),
2731 VA.getLocMemOffset(), false);
2735 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2736 VA.getLocMemOffset(), true);
2740 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
9543 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9544 std::string AsmStr = IA->getAsmString();
9558 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
9843 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {